f4exb
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6533df15f5
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Sample source FIFO: limit read count to FIFO size
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2019-11-17 03:16:50 +01:00 |
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f4exb
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3b74153ec6
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SampleSourceFifo refactoring and Tx code reorganization
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2019-11-15 01:05:32 +01:00 |
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f4exb
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e6a929470f
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Renamed SampleSourceFifo to SampleSourceFifoDB to mark double buffered nature of FIFO
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2019-11-02 11:03:07 +01:00 |
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f4exb
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7a1b727a36
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MIMO: device engine Tx handling (1)
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2019-10-19 05:07:40 +02:00 |
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f4exb
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68e4eaac68
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PVS-Studio analys fixes: core package minor issues
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2019-06-15 07:00:09 +02:00 |
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f4exb
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ddde7a925f
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MIMO: copied test source as multiple input. Adaptation of main classes
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2019-05-18 06:30:37 +02:00 |
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f4exb
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ba4c8d7a68
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Added the Local Source plugin
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2019-05-10 13:20:30 +02:00 |
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f4exb
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fc49bd2855
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ixed incomplete copyright headers (3): sdrbase
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2019-04-11 14:32:15 +02:00 |
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f4exb
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f01b90094b
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PVS-Studio static analysis corrections (1) issue #137
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2018-02-21 18:54:59 +01:00 |
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f4exb
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9a2ae892ed
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Sample source FIFO: moved emit data write at top of method so that samples can be written with no delay
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2018-01-02 01:04:04 +01:00 |
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f4exb
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09856b5941
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Sample source FIFO: write ahead the exact same amount of samples that were read. This smoothes out the process and avoids hickups
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2017-01-09 02:13:27 +01:00 |
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f4exb
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5598265e66
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Multiple modulators support: works with two modulators
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2016-12-26 12:11:51 +01:00 |
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f4exb
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e05822ba02
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Implement own FIFO in BasebandSampleSource. SampleSourceFIFO: remove useless chunk size completely and set initial fill to only half the FIFO size
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2016-12-23 14:29:42 +01:00 |
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f4exb
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1afd8df5f9
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Modulators: changed single Tx channel samples feed handling
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2016-12-22 23:39:06 +01:00 |
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f4exb
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441c2c1817
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Send number of samples to write in the writeData signal. Ask for half the buffer size when more than half of it is consumed
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2016-12-21 02:24:49 +01:00 |
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f4exb
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0fc6d95357
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Tx ph.1: fixed read pointer management when getting new samples
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2016-10-25 03:31:36 +02:00 |
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f4exb
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ee55747c0b
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Tx ph.1: FileSink: set sample source FIFO size depending on sample rate
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2016-10-25 02:34:29 +02:00 |
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f4exb
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289c1a203f
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Tx ph.1: Sample source FIFO read with signal. Use a specific spectrum sink (vis) reference in Device sink engine for main spectrum rendering
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2016-10-24 18:06:44 +02:00 |
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f4exb
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8f70840561
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Tx ph.1: fixed sample source FIFO
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2016-10-23 23:27:19 +02:00 |
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f4exb
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4e446b9c7a
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Tx ph.1: fixed source sink initialization
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2016-10-23 14:14:32 +02:00 |
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f4exb
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4b02072fe4
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Tx ph.1: add Tx tab (2). Fixed core dump
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2016-10-22 05:07:48 +02:00 |
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f4exb
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52b618469c
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Tx ph.1: refactored source sample FIFO. StarUML model: added Tx classes
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2016-10-15 09:53:06 +02:00 |
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f4exb
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6e82cb37b8
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Tx support: added a sample source FIFO class
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2016-10-10 01:13:12 +02:00 |
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