13 Commits

Author	SHA1	Message	Date
f4exb	7015fb97d2	Put intrinsics in their own templatized classes	2016-11-07 04:16:02 +01:00
f4exb	63d6eea066	Use more precise SIMD flags and detect actual x86_64 SIMD features	2016-11-07 00:42:57 +01:00
f4exb	dbbbfa12ee	Changed USE_SIMD flag to USE_SSE	2016-11-06 02:08:38 +01:00
f4exb	bc3dfb19cd	IntHalfBandFilterEO2: use dual forward and backward buffers to avoid byte shuffling in SIMD instructions. Implemented in the up channelizer	2016-11-06 01:07:13 +01:00
f4exb	f2a50c0c0f	Use even/odd FIR filter half band interpolator only if SIMD is available	2016-11-04 22:47:09 +01:00
f4exb	9f74c82715	IntHalfBand FIR filter SSE optimizations	2016-11-04 01:12:39 +01:00
f4exb	5d5593bda7	Tx ph.2: put the double buffered FIR interpolator and decimator in its own class	2016-11-01 15:02:50 +01:00
f4exb	bd4d224166	Tx ph.2: IntHalfBandFilter: use double buffer technique for interpolation. Use it with the UpChannelizer and increase order to 96 for better spur rejection. Moreover it is still more CPU efficient	2016-11-01 05:54:25 +01:00
f4exb	004cbcb060	Tx ph.2: UpChannelizer: use order 64 filter as longer orders do not improve image rejection	2016-10-31 00:33:20 +01:00
f4exb	f5bbbb7cab	Tx ph.2: UpChannelizer: allow any sample rate	2016-10-30 22:01:20 +01:00
f4exb	91315913b4	Tx ph.2: change UpChannelizer filter chain from std::list to std::vector	2016-10-30 18:22:33 +01:00
f4exb	4a001350d3	Tx ph.2: Templatized IntHalfbandFilter and improved coefficients. Changed to order 80 for upsamplers and 48 for downsamplers	2016-10-29 17:01:02 +02:00
f4exb	b56c2d9a2c	Tx ph.1: new classes (1)	2016-10-17 08:58:49 +02:00