f4exb
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b224e42ef0
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Windows: MSVC2017: adapt more channel plugin modules (1)
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2018-11-13 17:29:34 +01:00 |
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f4exb
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72e29fd3f8
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Moved export.h file to root of exports directory and removed util
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2018-03-20 13:49:21 +01:00 |
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f4exb
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980192548d
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Adapt to MSVC linker: removed SDRANGEL_API
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2018-03-03 21:19:59 +01:00 |
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f4exb
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c22d146376
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Adapt to MSVC linker
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2018-03-03 20:23:38 +01:00 |
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f4exb
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61a16eade9
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Use always 16 bit DSP on Tx side
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2018-01-22 10:46:57 +01:00 |
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f4exb
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bacc6659b0
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24 bit DSP: use a different define for Tx chain so that it can stay on 16 bit DSP
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2018-01-22 03:00:08 +01:00 |
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f4exb
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732561152b
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24 bit DSP fix
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2018-01-22 02:49:06 +01:00 |
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f4exb
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ad219d50cc
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Implemented 24 bit internal DSP (with bugs ...)
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2018-01-21 21:48:36 +01:00 |
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f4exb
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08ce7f423b
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Templatize the accumulator type of integer half-band filters (non SIMD)
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2018-01-21 19:39:51 +01:00 |
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f4exb
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c6083ea6f4
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Down/Up channelizers: enqeue MsgChannelizerNotification to sample sink/source instead of processing it directly
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2017-12-29 05:14:40 +01:00 |
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f4exb
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f6bc9daf8e
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UpChannelizer: pass baseband sample rate in notification message
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2017-08-06 17:10:29 +02:00 |
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f4exb
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e02ac85e50
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All modulators: use buffer for input audio that is always in use while generation is running. This fixes lockup problem reported in issue #11
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2016-12-26 01:39:34 +01:00 |
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f4exb
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f74e3b83a7
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Modulators: changed single Tx channel samples feed handling. Pure virtual function is useless
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2016-12-22 23:45:56 +01:00 |
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f4exb
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1afd8df5f9
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Modulators: changed single Tx channel samples feed handling
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2016-12-22 23:39:06 +01:00 |
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f4exb
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7015fb97d2
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Put intrinsics in their own templatized classes
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2016-11-07 04:16:02 +01:00 |
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f4exb
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63d6eea066
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Use more precise SIMD flags and detect actual x86_64 SIMD features
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2016-11-07 00:42:57 +01:00 |
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f4exb
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dbbbfa12ee
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Changed USE_SIMD flag to USE_SSE
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2016-11-06 02:08:38 +01:00 |
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f4exb
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bc3dfb19cd
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IntHalfBandFilterEO2: use dual forward and backward buffers to avoid byte shuffling in SIMD instructions. Implemented in the up channelizer
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2016-11-06 01:07:13 +01:00 |
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f4exb
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f2a50c0c0f
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Use even/odd FIR filter half band interpolator only if SIMD is available
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2016-11-04 22:47:09 +01:00 |
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f4exb
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9f74c82715
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IntHalfBand FIR filter SSE optimizations
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2016-11-04 01:12:39 +01:00 |
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f4exb
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5d5593bda7
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Tx ph.2: put the double buffered FIR interpolator and decimator in its own class
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2016-11-01 15:02:50 +01:00 |
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f4exb
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bd4d224166
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Tx ph.2: IntHalfBandFilter: use double buffer technique for interpolation. Use it with the UpChannelizer and increase order to 96 for better spur rejection. Moreover it is still more CPU efficient
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2016-11-01 05:54:25 +01:00 |
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f4exb
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004cbcb060
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Tx ph.2: UpChannelizer: use order 64 filter as longer orders do not improve image rejection
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2016-10-31 00:33:20 +01:00 |
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f4exb
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f5bbbb7cab
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Tx ph.2: UpChannelizer: allow any sample rate
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2016-10-30 22:01:20 +01:00 |
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f4exb
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91315913b4
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Tx ph.2: change UpChannelizer filter chain from std::list to std::vector
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2016-10-30 18:22:33 +01:00 |
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f4exb
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4a001350d3
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Tx ph.2: Templatized IntHalfbandFilter and improved coefficients. Changed to order 80 for upsamplers and 48 for downsamplers
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2016-10-29 17:01:02 +02:00 |
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f4exb
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b56c2d9a2c
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Tx ph.1: new classes (1)
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2016-10-17 08:58:49 +02:00 |
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