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clk: qcom: gpucc-blair: Scale both cx and gx rails for gfx3d clock

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There is a requirement to scale both CX and GX rails during the gpu core
clock scaling, thus add the corresponding vdd data.

Change-Id: Ib27f4697a84ece1d0d1ce2b5297c03bf8ed955c6
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
This commit is contained in:
Taniya Das 2021-12-03 15:00:45 +05:30 committed by Gerrit - the friendly Code Review server
parent 97db20de99
commit 1cdfc65d53
2 changed files with 30 additions and 3 deletions
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20
drivers/clk/qcom/gpucc-blair.c
View File

@ -23,12 +23,10 @@
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_gx, VDD_HIGH_L1 + 1, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_gx, VDD_NUM, 2, vdd_gx_corner);
static struct clk_vdd_class *gpu_cc_blair_regulators[] = {
&vdd_cx,
&vdd_mx,
&vdd_gx,
};
enum {
@ -468,6 +466,22 @@ static int gpu_cc_blair_probe(struct platform_device *pdev)
struct regmap *regmap;
int ret;
vdd_gx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gx");
if (IS_ERR(vdd_gx.regulator[0])) {
if (!(PTR_ERR(vdd_gx.regulator[0]) == -EPROBE_DEFER))
dev_err(&pdev->dev, "Unable to get vdd_gx regulator\n");
return PTR_ERR(vdd_gx.regulator[0]);
}
vdd_gx.regulator[1] = devm_regulator_get(&pdev->dev, "vdd_cx");
if (IS_ERR(vdd_gx.regulator[1])) {
if (!(PTR_ERR(vdd_gx.regulator[1]) == -EPROBE_DEFER))
dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
return PTR_ERR(vdd_gx.regulator[1]);
}
vdd_cx.regulator[0] = vdd_gx.regulator[1];
regmap = qcom_cc_map(pdev, &gpu_cc_blair_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);

13
drivers/clk/qcom/vdd-level-holi.h
View File

@ -32,4 +32,17 @@ static int vdd_corner[] = {
[VDD_HIGH_L1] = RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,
};
static int vdd_gx_corner[] = {
0, 0,
RPM_SMD_REGULATOR_LEVEL_MIN_SVS, RPM_SMD_REGULATOR_LEVEL_MIN_SVS,
RPM_SMD_REGULATOR_LEVEL_LOW_SVS, RPM_SMD_REGULATOR_LEVEL_LOW_SVS,
RPM_SMD_REGULATOR_LEVEL_SVS, RPM_SMD_REGULATOR_LEVEL_SVS,
RPM_SMD_REGULATOR_LEVEL_SVS_PLUS, RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,
RPM_SMD_REGULATOR_LEVEL_NOM, RPM_SMD_REGULATOR_LEVEL_NOM,
RPM_SMD_REGULATOR_LEVEL_NOM_PLUS, RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,
RPM_SMD_REGULATOR_LEVEL_TURBO, RPM_SMD_REGULATOR_LEVEL_TURBO,
RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR, RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,
};
#endif