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arm64: dts: lahaina: configure gpio47 as qupv3_se10_spi_sleep_cs

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Change-Id: I7496e7eb517a48a77ff9999dd5db8ce3d4e85e71
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Arian 2022-01-29 16:18:18 +01:00 committed by Giovanni Ricca
parent 92e1803495
commit 20c0591c0e
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2 changed files with 14 additions and 3 deletions
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15
arch/arm64/boot/dts/vendor/qcom/lahaina-pinctrl.dtsi vendored
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@ -831,13 +831,24 @@
qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
mux { mux {
pins = "gpio44", "gpio45", pins = "gpio44", "gpio45",
"gpio46", "gpio47"; "gpio46";
function = "gpio"; function = "gpio";
}; };
config { config {
pins = "gpio44", "gpio45", pins = "gpio44", "gpio45",
"gpio46", "gpio47"; "gpio46";
drive-strength = <6>;
bias-disable;
};
};
qupv3_se10_spi_sleep_cs: qupv3_se10_spi_sleep_cs {
mux {
pins = "gpio47";
function = "gpio";
};
config {
pins = "gpio47";
drive-strength = <6>; drive-strength = <6>;
bias-disable; bias-disable;
}; };

2
arch/arm64/boot/dts/vendor/qcom/lahaina-qupv3.dtsi vendored
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@ -557,7 +557,7 @@
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_spi_active>; pinctrl-0 = <&qupv3_se10_spi_active>;
pinctrl-1 = <&qupv3_se10_spi_sleep>; pinctrl-1 = <&qupv3_se10_spi_sleep &qupv3_se10_spi_sleep_cs>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>; qcom,wrapper-core = <&qupv3_1>;