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audio: asoc: Import cs35l45 codec

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From branch: redwood-s-oss

Change-Id: I60fe2293d8f6d8b4c78b6d5e2198f08d8d5fd9b8
This commit is contained in:
Giovanni Ricca 2023-01-29 02:32:24 +05:30
parent 15ffae710c
commit 500d3aaa20
No known key found for this signature in database
10 changed files with 11050 additions and 0 deletions
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110
techpack/audio/asoc/codecs/cs35l45/Kbuild Normal file
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# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_KONA), y)
include $(AUDIO_ROOT)/config/konaauto.conf
INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
export
INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi/audio
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ CS35L45 ############
# for CS35L45 Codec
ifdef CONFIG_SND_SOC_CS35L45
CS35L45_OBJS += cs35l45.o
CS35L45_OBJS += cs35l45-i2c.o
CS35L45_OBJS += cs35l45-tables.o
CS35L45_OBJS += wm_adsp.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
EXTRA_CFLAGS += $(INCS)
CDEFINES += -DCONFIG_AUDIO_SMARTPA_STEREO
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_CS35L45) += cs35l45_dlkm.o
cs35l45_dlkm-y := $(CS35L45_OBJS)
# inject some build related information
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

106
techpack/audio/asoc/codecs/cs35l45/cs35l45-i2c.c Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* cs35l45-i2c.c -- CS35L45 I2C driver
*
* Copyright 2019 Cirrus Logic, Inc.
*
* Author: James Schulman <james.schulman@cirrus.com>
*
*/
#define DEBUG
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regulator/consumer.h>
#include "wm_adsp.h"
#include "cs35l45.h"
#include "cs35l45_user.h"
static struct regmap_config cs35l45_regmap = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = CS35L45_REGSTRIDE,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L45_LASTREG,
.reg_defaults = cs35l45_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l45_reg),
.volatile_reg = cs35l45_volatile_reg,
.readable_reg = cs35l45_readable_reg,
.cache_type = REGCACHE_RBTREE,
};
static int cs35l45_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct cs35l45_private *cs35l45;
struct device *dev = &client->dev;
int ret;
cs35l45 = devm_kzalloc(dev, sizeof(struct cs35l45_private), GFP_KERNEL);
if (cs35l45 == NULL)
return -ENOMEM;
i2c_set_clientdata(client, cs35l45);
cs35l45->regmap = devm_regmap_init_i2c(client, &cs35l45_regmap);
if (IS_ERR(cs35l45->regmap)) {
ret = PTR_ERR(cs35l45->regmap);
dev_err(dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
cs35l45->dev = dev;
cs35l45->irq = client->irq;
cs35l45->wksrc = CS35L45_WKSRC_I2C;
cs35l45->i2c_addr = client->addr;
ret = cs35l45_probe(cs35l45);
if (ret < 0) {
dev_err(dev, "Failed device probe: %d\n", ret);
return ret;
}
usleep_range(2000, 2100);
ret = cs35l45_initialize(cs35l45);
if (ret < 0) {
dev_err(dev, "Failed device initialization: %d\n", ret);
return ret;
}
return 0;
}
static int cs35l45_i2c_remove(struct i2c_client *client)
{
struct cs35l45_private *cs35l45 = i2c_get_clientdata(client);
return cs35l45_remove(cs35l45);
}
static const struct of_device_id cs35l45_of_match[] = {
{.compatible = "cirrus,cs35l45"},
{},
};
MODULE_DEVICE_TABLE(of, cs35l45_of_match);
static const struct i2c_device_id cs35l45_id_i2c[] = {
{"cs35l45", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, cs35l45_id_i2c);
static struct i2c_driver cs35l45_i2c_driver = {
.driver = {
.name = "cs35l45",
.of_match_table = cs35l45_of_match,
},
.id_table = cs35l45_id_i2c,
.probe = cs35l45_i2c_probe,
.remove = cs35l45_i2c_remove,
};
module_i2c_driver(cs35l45_i2c_driver);
MODULE_DESCRIPTION("I2C CS35L45 driver");
MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
MODULE_LICENSE("GPL");

105
techpack/audio/asoc/codecs/cs35l45/cs35l45-spi.c Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* cs35l45-spi.c -- CS35L45 SPI driver
*
* Copyright 2019 Cirrus Logic, Inc.
*
* Author: James Schulman <james.schulman@cirrus.com>
*
*/
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include "wm_adsp.h"
#include "cs35l45.h"
#include "cs35l45_user.h"
static struct regmap_config cs35l45_regmap = {
.reg_bits = 32,
.val_bits = 32,
.pad_bits = 16,
.reg_stride = CS35L45_REGSTRIDE,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS35L45_LASTREG,
.reg_defaults = cs35l45_reg,
.num_reg_defaults = ARRAY_SIZE(cs35l45_reg),
.volatile_reg = cs35l45_volatile_reg,
.readable_reg = cs35l45_readable_reg,
.cache_type = REGCACHE_RBTREE,
};
static int cs35l45_spi_probe(struct spi_device *spi)
{
struct cs35l45_private *cs35l45;
struct device *dev = &spi->dev;
int ret;
cs35l45 = devm_kzalloc(dev, sizeof(struct cs35l45_private), GFP_KERNEL);
if (cs35l45 == NULL)
return -ENOMEM;
spi_set_drvdata(spi, cs35l45);
cs35l45->regmap = devm_regmap_init_spi(spi, &cs35l45_regmap);
if (IS_ERR(cs35l45->regmap)) {
ret = PTR_ERR(cs35l45->regmap);
dev_err(dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
cs35l45->dev = dev;
cs35l45->irq = spi->irq;
cs35l45->wksrc = CS35L45_WKSRC_SPI;
ret = cs35l45_probe(cs35l45);
if (ret < 0) {
dev_err(dev, "Failed device probe: %d\n", ret);
return ret;
}
usleep_range(2000, 2100);
ret = cs35l45_initialize(cs35l45);
if (ret < 0) {
dev_err(dev, "Failed device initialization: %d\n", ret);
return ret;
}
return 0;
}
static int cs35l45_spi_remove(struct spi_device *spi)
{
struct cs35l45_private *cs35l45 = spi_get_drvdata(spi);
return cs35l45_remove(cs35l45);
}
static const struct of_device_id cs35l45_of_match[] = {
{.compatible = "cirrus,cs35l45"},
{},
};
MODULE_DEVICE_TABLE(of, cs35l45_of_match);
static const struct spi_device_id cs35l45_id_spi[] = {
{"cs35l45", 0},
{}
};
MODULE_DEVICE_TABLE(spi, cs35l45_id_spi);
static struct spi_driver cs35l45_spi_driver = {
.driver = {
.name = "cs35l45",
.of_match_table = cs35l45_of_match,
},
.id_table = cs35l45_id_spi,
.probe = cs35l45_spi_probe,
.remove = cs35l45_spi_remove,
};
module_spi_driver(cs35l45_spi_driver);
MODULE_DESCRIPTION("SPI CS35L45 driver");
MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
MODULE_LICENSE("GPL");

755
techpack/audio/asoc/codecs/cs35l45/cs35l45-tables.c Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
*
* Copyright 2019 Cirrus Logic, Inc.
*
* Author: James Schulman <james.schulman@cirrus.com>
*
*/
#include <linux/module.h>
#include <linux/regulator/consumer.h>
#include "wm_adsp.h"
#include "cs35l45.h"
#include "cs35l45_user.h"
const struct reg_default cs35l45_reg[CS35L45_MAX_CACHE_REG] = {
{CS35L45_BLOCK_ENABLES, 0x00003323},
{CS35L45_BLOCK_ENABLES2, 0x00000010},
{CS35L45_GLOBAL_OVERRIDES, 0x00000002},
{CS35L45_GLOBAL_SYNC, 0x00000000},
{CS35L45_ERROR_RELEASE, 0x00000000},
{CS35L45_SYNC_GPIO1, 0x00000007},
{CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005},
{CS35L45_GPIO3, 0x00000005},
{CS35L45_GPIO_GLOBAL_ENABLE_CONTROL, 0x00000000},
{CS35L45_PWRMGT_CTL, 0x00000000},
{CS35L45_WAKESRC_CTL, 0x00000008},
{CS35L45_WKI2C_CTL, 0x00000030},
{CS35L45_PWRMGT_STS, 0x00000000},
{CS35L45_REFCLK_INPUT, 0x00000510},
{CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003},
{CS35L45_SWIRE_CLK_CTRL, 0x00000000},
{CS35L45_BOOST_VOLTAGE_CFG, 0x000001BE},
{CS35L45_BOOST_CCM_CFG, 0xF0000001},
{CS35L45_BOOST_DCM_CFG, 0x08710200},
{CS35L45_BOOST_LPMODE_CFG, 0x00000002},
{CS35L45_BOOST_RAMP_CFG, 0x0000004A},
{CS35L45_BOOST_STARTUP_CFG, 0x0000831D},
{CS35L45_BOOST_OV_CFG, 0x005400D0},
{CS35L45_BOOST_UV_CFG, 0x00000570},
{CS35L45_BOOST_STATUS, 0x00000001},
{CS35L45_BST_BPE_INST_THLD, 0x5A46321E},
{CS35L45_BST_BPE_INST_ILIM, 0x3C140C04},
{CS35L45_BST_BPE_INST_SS_ILIM, 0x1C080400},
{CS35L45_BST_BPE_INST_ATK_RATE, 0x06060600},
{CS35L45_BST_BPE_INST_HOLD_TIME, 0x02020202},
{CS35L45_BST_BPE_INST_RLS_RATE, 0x06060606},
{CS35L45_BST_BPE_MISC_CONFIG, 0x00000000},
{CS35L45_BST_BPE_IL_LIM_THLD, 0x0006022C},
{CS35L45_BST_BPE_IL_LIM_DLY, 0x0000040C},
{CS35L45_BST_BPE_IL_LIM_ATK_RATE, 0x00000000},
{CS35L45_BST_BPE_IL_LIM_RLS_RATE, 0x00000000},
{CS35L45_BST_BPE_INST_STATUS, 0x0000005A},
{CS35L45_MONITOR_FILT, 0x00000000},
{CS35L45_IMON_COMP, 0x00000036},
{CS35L45_STATUS, 0x00000010},
{CS35L45_MON_VALUE, 0x00000000},
{CS35L45_ASP_ENABLES1, 0x00000000},
{CS35L45_ASP_CONTROL1, 0x00000028},
{CS35L45_ASP_CONTROL2, 0x18180200},
{CS35L45_ASP_CONTROL3, 0x00000002},
{CS35L45_ASP_FRAME_CONTROL1, 0x03020100},
{CS35L45_ASP_FRAME_CONTROL2, 0x00000004},
{CS35L45_ASP_FRAME_CONTROL5, 0x00000100},
{CS35L45_ASP_DATA_CONTROL1, 0x00000018},
{CS35L45_ASP_DATA_CONTROL5, 0x00000018},
{CS35L45_DACPCM1_INPUT, 0x00000008},
{CS35L45_ASPTX1_INPUT, 0x00000018},
{CS35L45_ASPTX2_INPUT, 0x00000019},
{CS35L45_ASPTX3_INPUT, 0x00000020},
{CS35L45_ASPTX4_INPUT, 0x00000021},
{CS35L45_ASPTX5_INPUT, 0x00000048},
{CS35L45_DSP1RX1_INPUT, 0x00000008},
{CS35L45_DSP1RX2_INPUT, 0x00000009},
{CS35L45_DSP1RX3_INPUT, 0x00000018},
{CS35L45_DSP1RX4_INPUT, 0x00000019},
{CS35L45_DSP1RX5_INPUT, 0x00000020},
{CS35L45_DSP1RX6_INPUT, 0x00000028},
{CS35L45_DSP1RX7_INPUT, 0x0000003A},
{CS35L45_DSP1RX8_INPUT, 0x00000028},
{CS35L45_NGATE1_INPUT, 0x00000008},
{CS35L45_NGATE2_INPUT, 0x00000009},
{CS35L45_SWIRE_PORT1_CH1_INPUT, 0x00000018},
{CS35L45_SWIRE_PORT1_CH2_INPUT, 0x00000019},
{CS35L45_SWIRE_PORT1_CH3_INPUT, 0x00000020},
{CS35L45_SWIRE_PORT1_CH4_INPUT, 0x00000021},
{CS35L45_SWIRE_PORT1_CH5_INPUT, 0x00000048},
{CS35L45_AMP_ERR_VOL_SEL, 0x00000001},
{CS35L45_TEMP_WARN_THRESHOLD, 0x00000003},
{CS35L45_TEMP_WARN_CONFIG, 0x00522183},
{CS35L45_TEMP_WARN_TRIG_AUTO, 0x00000010},
{CS35L45_TEMP_WARN_STATUS, 0x00000000},
{CS35L45_BPE_INST_THLD, 0x5A46321E},
{CS35L45_BPE_INST_ATTN, 0x060C1218},
{CS35L45_BPE_INST_ATK_RATE, 0x06060606},
{CS35L45_BPE_INST_HOLD_TIME, 0x02020202},
{CS35L45_BPE_INST_RLS_RATE, 0x05050505},
{CS35L45_BPE_MISC_CONFIG, 0x00008000},
{CS35L45_BPE_INST_STATUS, 0x0000005A},
{CS35L45_HVLV_CONFIG, 0x00440017},
{CS35L45_LDPM_CONFIG, 0x00013636},
{CS35L45_CLASSH_CONFIG1, 0x02000B04},
{CS35L45_CLASSH_CONFIG2, 0x009600FA},
{CS35L45_CLASSH_CONFIG3, 0x00000000},
{CS35L45_AUD_MEM, 0x00000007},
{CS35L45_AMP_PCM_CONTROL, 0x00100000},
{CS35L45_AMP_GAIN, 0x00002300},
{CS35L45_DAC_MSM_CONFIG, 0x00000020},
{CS35L45_AMP_OUTPUT_MUTE, 0x00000000},
{CS35L45_AMP_OUTPUT_DRV, 0x00000040},
{CS35L45_ALIVE_DCIN_WD, 0x00000263},
{CS35L45_IRQ1_CFG, 0x00000000},
{CS35L45_IRQ2_CFG, 0x00000000},
{CS35L45_GPIO1_CTRL1, 0x81000001},
{CS35L45_GPIO2_CTRL1, 0x81000001},
{CS35L45_GPIO3_CTRL1, 0x81000001},
{CS35L45_MIXER_NGATE_CH1_CFG, 0x00000303},
{CS35L45_MIXER_NGATE_CH2_CFG, 0x00000303},
{CS35L45_CLOCK_DETECT_1, 0x00000030},
};
bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L45_DEVID:
case CS35L45_REVID:
case CS35L45_RELID:
case CS35L45_OTPID:
case CS35L45_SFT_RESET:
case CS35L45_GLOBAL_ENABLES:
case CS35L45_BLOCK_ENABLES:
case CS35L45_BLOCK_ENABLES2:
case CS35L45_GLOBAL_OVERRIDES:
case CS35L45_GLOBAL_SYNC:
case CS35L45_ERROR_RELEASE:
case CS35L45_CHIP_STATUS:
case CS35L45_REG_2114:
case CS35L45_REG_225C:
case CS35L45_SYNC_GPIO1:
case CS35L45_INTB_GPIO2_MCLK_REF:
case CS35L45_GPIO3:
case CS35L45_GPIO_GLOBAL_ENABLE_CONTROL:
case CS35L45_PWRMGT_CTL:
case CS35L45_WAKESRC_CTL:
case CS35L45_WKI2C_CTL:
case CS35L45_PWRMGT_STS:
case CS35L45_REFCLK_INPUT:
case CS35L45_REG_2C08:
case CS35L45_GLOBAL_SAMPLE_RATE:
case CS35L45_SWIRE_CLK_CTRL:
case CS35L45_SYNC_TX_RX_ENABLES:
case CS35L45_SYNC_SW_TX_ID:
case CS35L45_BOOST_VOLTAGE_CFG:
case CS35L45_BOOST_CCM_CFG:
case CS35L45_BOOST_DCM_CFG:
case CS35L45_BOOST_LPMODE_CFG:
case CS35L45_BOOST_RAMP_CFG:
case CS35L45_BOOST_STARTUP_CFG:
case CS35L45_BOOST_OV_CFG:
case CS35L45_BOOST_UV_CFG:
case CS35L45_BOOST_STATUS:
case CS35L45_BST_BPE_INST_THLD:
case CS35L45_BST_BPE_INST_ILIM:
case CS35L45_BST_BPE_INST_SS_ILIM:
case CS35L45_BST_BPE_INST_ATK_RATE:
case CS35L45_BST_BPE_INST_HOLD_TIME:
case CS35L45_BST_BPE_INST_RLS_RATE:
case CS35L45_BST_BPE_MISC_CONFIG:
case CS35L45_BST_BPE_IL_LIM_THLD:
case CS35L45_BST_BPE_IL_LIM_DLY:
case CS35L45_BST_BPE_IL_LIM_ATK_RATE:
case CS35L45_BST_BPE_IL_LIM_RLS_RATE:
case CS35L45_BST_BPE_INST_STATUS:
case CS35L45_MONITOR_FILT:
case CS35L45_IMON_COMP:
case CS35L45_STATUS:
case CS35L45_MON_VALUE:
case CS35L45_ASP_ENABLES1:
case CS35L45_ASP_CONTROL1:
case CS35L45_ASP_CONTROL2:
case CS35L45_ASP_CONTROL3:
case CS35L45_ASP_FRAME_CONTROL1:
case CS35L45_ASP_FRAME_CONTROL2:
case CS35L45_ASP_FRAME_CONTROL5:
case CS35L45_ASP_DATA_CONTROL1:
case CS35L45_ASP_DATA_CONTROL5:
case CS35L45_DACPCM1_INPUT:
case CS35L45_MIXER_PILOT0_INPUT:
case CS35L45_ASPTX1_INPUT:
case CS35L45_ASPTX2_INPUT:
case CS35L45_ASPTX3_INPUT:
case CS35L45_ASPTX4_INPUT:
case CS35L45_ASPTX5_INPUT:
case CS35L45_DSP1RX1_INPUT:
case CS35L45_DSP1RX2_INPUT:
case CS35L45_DSP1RX3_INPUT:
case CS35L45_DSP1RX4_INPUT:
case CS35L45_DSP1RX5_INPUT:
case CS35L45_DSP1RX6_INPUT:
case CS35L45_DSP1RX7_INPUT:
case CS35L45_DSP1RX8_INPUT:
case CS35L45_NGATE1_INPUT:
case CS35L45_NGATE2_INPUT:
case CS35L45_SWIRE_PORT1_CH1_INPUT:
case CS35L45_SWIRE_PORT1_CH2_INPUT:
case CS35L45_SWIRE_PORT1_CH3_INPUT:
case CS35L45_SWIRE_PORT1_CH4_INPUT:
case CS35L45_SWIRE_PORT1_CH5_INPUT:
case CS35L45_AMP_ERR_VOL_SEL:
case CS35L45_TEMP_WARN_THRESHOLD:
case CS35L45_TEMP_WARN_CONFIG:
case CS35L45_TEMP_WARN_TRIG_AUTO:
case CS35L45_TEMP_WARN_STATUS:
case CS35L45_BPE_INST_THLD:
case CS35L45_BPE_INST_ATTN:
case CS35L45_BPE_INST_ATK_RATE:
case CS35L45_BPE_INST_HOLD_TIME:
case CS35L45_BPE_INST_RLS_RATE:
case CS35L45_BPE_MISC_CONFIG:
case CS35L45_BPE_INST_STATUS:
case CS35L45_HVLV_CONFIG:
case CS35L45_LDPM_CONFIG:
case CS35L45_CLASSH_CONFIG1:
case CS35L45_CLASSH_CONFIG2:
case CS35L45_CLASSH_CONFIG3:
case CS35L45_AUD_MEM:
case CS35L45_AMP_PCM_CONTROL:
case CS35L45_AMP_GAIN:
case CS35L45_DAC_MSM_CONFIG:
case CS35L45_AMP_OUTPUT_MUTE:
case CS35L45_AMP_OUTPUT_DRV:
case CS35L45_ALIVE_DCIN_WD:
case CS35L45_IRQ1_CFG:
case CS35L45_IRQ1_STATUS:
case CS35L45_IRQ1_EINT_1:
case CS35L45_IRQ1_EINT_2:
case CS35L45_IRQ1_EINT_3:
case CS35L45_IRQ1_EINT_4:
case CS35L45_IRQ1_EINT_5:
case CS35L45_IRQ1_EINT_7:
case CS35L45_IRQ1_EINT_8:
case CS35L45_IRQ1_EINT_18:
case CS35L45_IRQ1_STS_1:
case CS35L45_IRQ1_STS_2:
case CS35L45_IRQ1_STS_3:
case CS35L45_IRQ1_STS_4:
case CS35L45_IRQ1_STS_5:
case CS35L45_IRQ1_STS_7:
case CS35L45_IRQ1_STS_8:
case CS35L45_IRQ1_STS_18:
case CS35L45_IRQ1_MASK_1:
case CS35L45_IRQ1_MASK_2:
case CS35L45_IRQ1_MASK_3:
case CS35L45_IRQ1_MASK_4:
case CS35L45_IRQ1_MASK_5:
case CS35L45_IRQ1_MASK_7:
case CS35L45_IRQ1_MASK_8:
case CS35L45_IRQ1_MASK_18:
case CS35L45_IRQ1_EDGE_1:
case CS35L45_IRQ1_EDGE_4:
case CS35L45_IRQ1_POL_1:
case CS35L45_IRQ1_POL_2:
case CS35L45_IRQ1_POL_4:
case CS35L45_IRQ1_DB_3:
case CS35L45_IRQ2_CFG:
case CS35L45_IRQ2_STATUS:
case CS35L45_IRQ2_EINT_1:
case CS35L45_IRQ2_EINT_2:
case CS35L45_IRQ2_EINT_3:
case CS35L45_IRQ2_EINT_4:
case CS35L45_IRQ2_EINT_5:
case CS35L45_IRQ2_EINT_7:
case CS35L45_IRQ2_EINT_8:
case CS35L45_IRQ2_EINT_18:
case CS35L45_IRQ2_STS_1:
case CS35L45_IRQ2_STS_2:
case CS35L45_IRQ2_STS_3:
case CS35L45_IRQ2_STS_4:
case CS35L45_IRQ2_STS_5:
case CS35L45_IRQ2_STS_7:
case CS35L45_IRQ2_STS_8:
case CS35L45_IRQ2_STS_18:
case CS35L45_IRQ2_MASK_1:
case CS35L45_IRQ2_MASK_2:
case CS35L45_IRQ2_MASK_3:
case CS35L45_IRQ2_MASK_4:
case CS35L45_IRQ2_MASK_5:
case CS35L45_IRQ2_MASK_7:
case CS35L45_IRQ2_MASK_8:
case CS35L45_IRQ2_MASK_18:
case CS35L45_IRQ2_EDGE_1:
case CS35L45_IRQ2_EDGE_4:
case CS35L45_IRQ2_POL_1:
case CS35L45_IRQ2_POL_2:
case CS35L45_IRQ2_POL_4:
case CS35L45_IRQ2_DB_3:
case CS35L45_GPIO_STATUS1:
case CS35L45_GPIO1_CTRL1:
case CS35L45_GPIO2_CTRL1:
case CS35L45_GPIO3_CTRL1:
case CS35L45_MIXER_NGATE_CH1_CFG:
case CS35L45_MIXER_NGATE_CH2_CFG:
case CS35L45_DSP_MBOX_1:
case CS35L45_DSP_MBOX_2:
case CS35L45_DSP_MBOX_3:
case CS35L45_DSP_MBOX_4:
case CS35L45_DSP_MBOX_5:
case CS35L45_DSP_MBOX_6:
case CS35L45_DSP_MBOX_7:
case CS35L45_DSP_MBOX_8:
case CS35L45_DSP_VIRT1_MBOX_1:
case CS35L45_DSP_VIRT1_MBOX_2:
case CS35L45_DSP_VIRT1_MBOX_3:
case CS35L45_DSP_VIRT1_MBOX_4:
case CS35L45_DSP_VIRT1_MBOX_5:
case CS35L45_DSP_VIRT1_MBOX_6:
case CS35L45_DSP_VIRT1_MBOX_7:
case CS35L45_DSP_VIRT1_MBOX_8:
case CS35L45_DSP_VIRT2_MBOX_1:
case CS35L45_DSP_VIRT2_MBOX_2:
case CS35L45_DSP_VIRT2_MBOX_3:
case CS35L45_DSP_VIRT2_MBOX_4:
case CS35L45_DSP_VIRT2_MBOX_5:
case CS35L45_DSP_VIRT2_MBOX_6:
case CS35L45_DSP_VIRT2_MBOX_7:
case CS35L45_DSP_VIRT2_MBOX_8:
case CS35L45_CLOCK_DETECT_1:
case CS35L45_DSP1_SYS_ID:
case CS35L45_DSP1_CLOCK_FREQ:
case CS35L45_DSP1_RX1_RATE:
case CS35L45_DSP1_RX2_RATE:
case CS35L45_DSP1_RX3_RATE:
case CS35L45_DSP1_RX4_RATE:
case CS35L45_DSP1_RX5_RATE:
case CS35L45_DSP1_RX6_RATE:
case CS35L45_DSP1_RX7_RATE:
case CS35L45_DSP1_RX8_RATE:
case CS35L45_DSP1_TX1_RATE:
case CS35L45_DSP1_TX2_RATE:
case CS35L45_DSP1_TX3_RATE:
case CS35L45_DSP1_TX4_RATE:
case CS35L45_DSP1_TX5_RATE:
case CS35L45_DSP1_TX6_RATE:
case CS35L45_DSP1_TX7_RATE:
case CS35L45_DSP1_TX8_RATE:
case CS35L45_DSP1_SCRATCH1:
case CS35L45_DSP1_SCRATCH2:
case CS35L45_DSP1_SCRATCH3:
case CS35L45_DSP1_SCRATCH4:
case CS35L45_DSP1_CCM_CORE_CONTROL:
case CS35L45_DSP1_STREAM_ARB_MSTR1_CONFIG_0:
case CS35L45_DSP1_STREAM_ARB_TX1_CONFIG_0:
case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
return true;
default:
return false;
}
}
bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS35L45_DEVID:
case CS35L45_SFT_RESET:
case CS35L45_REVID:
case CS35L45_GLOBAL_ENABLES:
case CS35L45_BLOCK_ENABLES:
case CS35L45_BLOCK_ENABLES2:
case CS35L45_GLOBAL_OVERRIDES:
case CS35L45_CHIP_STATUS:
case CS35L45_PWRMGT_STS:
case CS35L45_SYNC_TX_RX_ENABLES:
case CS35L45_SYNC_SW_TX_ID:
case CS35L45_BOOST_CCM_CFG:
case CS35L45_BOOST_DCM_CFG:
case CS35L45_BOOST_OV_CFG:
case CS35L45_BOOST_STATUS:
case CS35L45_BST_BPE_INST_STATUS:
case CS35L45_STATUS:
case CS35L45_REG_2114:
case CS35L45_REG_225C:
case CS35L45_REG_2C08:
case CS35L45_MON_VALUE:
case CS35L45_LDPM_CONFIG:
case CS35L45_IRQ1_STATUS:
case CS35L45_IRQ1_EINT_1:
case CS35L45_IRQ1_EINT_2:
case CS35L45_IRQ1_EINT_3:
case CS35L45_IRQ1_EINT_4:
case CS35L45_IRQ1_EINT_5:
case CS35L45_IRQ1_EINT_7:
case CS35L45_IRQ1_EINT_8:
case CS35L45_IRQ1_EINT_18:
case CS35L45_IRQ1_STS_1:
case CS35L45_IRQ1_STS_2:
case CS35L45_IRQ1_STS_3:
case CS35L45_IRQ1_STS_4:
case CS35L45_IRQ1_STS_5:
case CS35L45_IRQ1_STS_7:
case CS35L45_IRQ1_STS_8:
case CS35L45_IRQ1_STS_18:
case CS35L45_IRQ2_STATUS:
case CS35L45_IRQ2_EINT_1:
case CS35L45_IRQ2_EINT_2:
case CS35L45_IRQ2_EINT_3:
case CS35L45_IRQ2_EINT_4:
case CS35L45_IRQ2_EINT_5:
case CS35L45_IRQ2_EINT_7:
case CS35L45_IRQ2_EINT_8:
case CS35L45_IRQ2_EINT_18:
case CS35L45_IRQ2_STS_1:
case CS35L45_IRQ2_STS_2:
case CS35L45_IRQ2_STS_3:
case CS35L45_IRQ2_STS_4:
case CS35L45_IRQ2_STS_5:
case CS35L45_IRQ2_STS_7:
case CS35L45_IRQ2_STS_8:
case CS35L45_IRQ2_STS_18:
case CS35L45_GPIO_STATUS1:
case CS35L45_DSP_MBOX_1:
case CS35L45_DSP_MBOX_2:
case CS35L45_DSP_MBOX_3:
case CS35L45_DSP_MBOX_4:
case CS35L45_DSP_MBOX_5:
case CS35L45_DSP_MBOX_6:
case CS35L45_DSP_MBOX_7:
case CS35L45_DSP_MBOX_8:
case CS35L45_DSP_VIRT1_MBOX_1:
case CS35L45_DSP_VIRT1_MBOX_2:
case CS35L45_DSP_VIRT1_MBOX_3:
case CS35L45_DSP_VIRT1_MBOX_4:
case CS35L45_DSP_VIRT1_MBOX_5:
case CS35L45_DSP_VIRT1_MBOX_6:
case CS35L45_DSP_VIRT1_MBOX_7:
case CS35L45_DSP_VIRT1_MBOX_8:
case CS35L45_DSP_VIRT2_MBOX_1:
case CS35L45_DSP_VIRT2_MBOX_2:
case CS35L45_DSP_VIRT2_MBOX_3:
case CS35L45_DSP_VIRT2_MBOX_4:
case CS35L45_DSP_VIRT2_MBOX_5:
case CS35L45_DSP_VIRT2_MBOX_6:
case CS35L45_DSP_VIRT2_MBOX_7:
case CS35L45_DSP_VIRT2_MBOX_8:
case CS35L45_DSP1_SCRATCH1:
case CS35L45_DSP1_SCRATCH2:
case CS35L45_DSP1_SCRATCH3:
case CS35L45_DSP1_SCRATCH4:
case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
return true;
default:
return false;
}
}
const struct cs35l45_pll_sysclk_config
cs35l45_pll_sysclk[CS35L45_MAX_PLL_CONFIGS] = {
{ 32768, 0x00 },
{ 8000, 0x01 },
{ 11025, 0x02 },
{ 12000, 0x03 },
{ 16000, 0x04 },
{ 22050, 0x05 },
{ 24000, 0x06 },
{ 32000, 0x07 },
{ 44100, 0x08 },
{ 48000, 0x09 },
{ 88200, 0x0A },
{ 96000, 0x0B },
{ 128000, 0x0C },
{ 176400, 0x0D },
{ 192000, 0x0E },
{ 256000, 0x0F },
{ 352800, 0x10 },
{ 384000, 0x11 },
{ 512000, 0x12 },
{ 705600, 0x13 },
{ 750000, 0x14 },
{ 768000, 0x15 },
{ 1000000, 0x16 },
{ 1024000, 0x17 },
{ 1200000, 0x18 },
{ 1411200, 0x19 },
{ 1500000, 0x1A },
{ 1536000, 0x1B },
{ 2000000, 0x1C },
{ 2048000, 0x1D },
{ 2400000, 0x1E },
{ 2822400, 0x1F },
{ 3000000, 0x20 },
{ 3072000, 0x21 },
{ 3200000, 0x22 },
{ 4000000, 0x23 },
{ 4096000, 0x24 },
{ 4800000, 0x25 },
{ 5644800, 0x26 },
{ 6000000, 0x27 },
{ 6144000, 0x28 },
{ 6250000, 0x29 },
{ 6400000, 0x2A },
{ 6500000, 0x2B },
{ 6750000, 0x2C },
{ 7526400, 0x2D },
{ 8000000, 0x2E },
{ 8192000, 0x2F },
{ 9600000, 0x30 },
{ 11289600, 0x31 },
{ 12000000, 0x32 },
{ 12288000, 0x33 },
{ 12500000, 0x34 },
{ 12800000, 0x35 },
{ 13000000, 0x36 },
{ 13500000, 0x37 },
{ 19200000, 0x38 },
{ 22579200, 0x39 },
{ 24000000, 0x3A },
{ 24576000, 0x3B },
{ 25000000, 0x3C },
{ 25600000, 0x3D },
{ 26000000, 0x3E },
{ 27000000, 0x3F },
};
const struct of_entry bst_bpe_inst_thld_map[BST_BPE_INST_LEVELS] = {
[L0] = {"bst-bpe-inst-thld", CS35L45_BST_BPE_INST_THLD,
CS35L45_BST_BPE_INST_L0_THLD_MASK,
CS35L45_BST_BPE_INST_L0_THLD_SHIFT},
[L1] = {"bst-bpe-inst-thld", CS35L45_BST_BPE_INST_THLD,
CS35L45_BST_BPE_INST_L1_THLD_MASK,
CS35L45_BST_BPE_INST_L1_THLD_SHIFT},
[L2] = {"bst-bpe-inst-thld", CS35L45_BST_BPE_INST_THLD,
CS35L45_BST_BPE_INST_L2_THLD_MASK,
CS35L45_BST_BPE_INST_L2_THLD_SHIFT},
[L3] = {"bst-bpe-inst-thld", CS35L45_BST_BPE_INST_THLD,
CS35L45_BST_BPE_INST_L3_THLD_MASK,
CS35L45_BST_BPE_INST_L3_THLD_SHIFT},
[L4] = {"bst-bpe-inst-thld", 0, 0, 0},
};
const struct of_entry bst_bpe_inst_ilim_map[BST_BPE_INST_LEVELS] = {
[L0] = {"bst-bpe-inst-ilim", 0, 0, 0},
[L1] = {"bst-bpe-inst-ilim", CS35L45_BST_BPE_INST_ILIM,
CS35L45_BST_BPE_INST_L1_ILIM_MASK,
CS35L45_BST_BPE_INST_L1_ILIM_SHIFT},
[L2] = {"bst-bpe-inst-ilim", CS35L45_BST_BPE_INST_ILIM,
CS35L45_BST_BPE_INST_L2_ILIM_MASK,
CS35L45_BST_BPE_INST_L2_ILIM_SHIFT},
[L3] = {"bst-bpe-inst-ilim", CS35L45_BST_BPE_INST_ILIM,
CS35L45_BST_BPE_INST_L3_ILIM_MASK,
CS35L45_BST_BPE_INST_L3_ILIM_SHIFT},
[L4] = {"bst-bpe-inst-ilim", CS35L45_BST_BPE_INST_ILIM,
CS35L45_BST_BPE_INST_L4_ILIM_MASK,
CS35L45_BST_BPE_INST_L4_ILIM_SHIFT},
};
const struct of_entry bst_bpe_inst_ss_ilim_map[BST_BPE_INST_LEVELS] = {
[L0] = {"bst-bpe-inst-ss-ilim", 0, 0, 0},
[L1] = {"bst-bpe-inst-ss-ilim", CS35L45_BST_BPE_INST_SS_ILIM,
CS35L45_BST_BPE_INST_L1_SS_ILIM_MASK,
CS35L45_BST_BPE_INST_L1_SS_ILIM_SHIFT},
[L2] = {"bst-bpe-inst-ss-ilim", CS35L45_BST_BPE_INST_SS_ILIM,
CS35L45_BST_BPE_INST_L2_SS_ILIM_MASK,
CS35L45_BST_BPE_INST_L2_SS_ILIM_SHIFT},
[L3] = {"bst-bpe-inst-ss-ilim", CS35L45_BST_BPE_INST_SS_ILIM,
CS35L45_BST_BPE_INST_L3_SS_ILIM_MASK,
CS35L45_BST_BPE_INST_L3_SS_ILIM_SHIFT},
[L4] = {"bst-bpe-inst-ss-ilim", CS35L45_BST_BPE_INST_SS_ILIM,
CS35L45_BST_BPE_INST_L4_SS_ILIM_MASK,
CS35L45_BST_BPE_INST_L4_SS_ILIM_SHIFT},
};
const struct of_entry bst_bpe_inst_atk_rate_map[BST_BPE_INST_LEVELS] = {
[L0] = {"bst-bpe-inst-atk-rate", 0, 0, 0},
[L1] = {"bst-bpe-inst-atk-rate", CS35L45_BST_BPE_INST_ATK_RATE,
CS35L45_BST_BPE_INST_L1_ATK_RATE_MASK,
CS35L45_BST_BPE_INST_L1_ATK_RATE_SHIFT},
[L2] = {"bst-bpe-inst-atk-rate", CS35L45_BST_BPE_INST_ATK_RATE,
CS35L45_BST_BPE_INST_L2_ATK_RATE_MASK,
CS35L45_BST_BPE_INST_L2_ATK_RATE_SHIFT},
[L3] = {"bst-bpe-inst-atk-rate", CS35L45_BST_BPE_INST_ATK_RATE,
CS35L45_BST_BPE_INST_L3_ATK_RATE_MASK,
CS35L45_BST_BPE_INST_L3_ATK_RATE_SHIFT},
[L4] = {"bst-bpe-inst-atk-rate", 0, 0, 0},
};
const struct of_entry bst_bpe_inst_hold_time_map[BST_BPE_INST_LEVELS] = {
[L0] = {"bst-bpe-inst-hold-time", CS35L45_BST_BPE_INST_HOLD_TIME,
CS35L45_BST_BPE_INST_L0_HOLD_TIME_MASK,
CS35L45_BST_BPE_INST_L0_HOLD_TIME_SHIFT},
[L1] = {"bst-bpe-inst-hold-time", CS35L45_BST_BPE_INST_HOLD_TIME,
CS35L45_BST_BPE_INST_L1_HOLD_TIME_MASK,
CS35L45_BST_BPE_INST_L1_HOLD_TIME_SHIFT},
[L2] = {"bst-bpe-inst-hold-time", CS35L45_BST_BPE_INST_HOLD_TIME,
CS35L45_BST_BPE_INST_L2_HOLD_TIME_MASK,
CS35L45_BST_BPE_INST_L2_HOLD_TIME_SHIFT},
[L3] = {"bst-bpe-inst-hold-time", CS35L45_BST_BPE_INST_HOLD_TIME,
CS35L45_BST_BPE_INST_L3_HOLD_TIME_MASK,
CS35L45_BST_BPE_INST_L3_HOLD_TIME_SHIFT},
[L4] = {"bst-bpe-inst-hold-time", 0, 0, 0},
};
const struct of_entry bst_bpe_inst_rls_rate_map[BST_BPE_INST_LEVELS] = {
[L0] = {"bst-bpe-inst-rls-rate", CS35L45_BST_BPE_INST_RLS_RATE,
CS35L45_BST_BPE_INST_L0_RLS_RATE_MASK,
CS35L45_BST_BPE_INST_L0_RLS_RATE_SHIFT},
[L1] = {"bst-bpe-inst-rls-rate", CS35L45_BST_BPE_INST_RLS_RATE,
CS35L45_BST_BPE_INST_L1_RLS_RATE_MASK,
CS35L45_BST_BPE_INST_L1_RLS_RATE_SHIFT},
[L2] = {"bst-bpe-inst-rls-rate", CS35L45_BST_BPE_INST_RLS_RATE,
CS35L45_BST_BPE_INST_L2_RLS_RATE_MASK,
CS35L45_BST_BPE_INST_L2_RLS_RATE_SHIFT},
[L3] = {"bst-bpe-inst-rls-rate", CS35L45_BST_BPE_INST_RLS_RATE,
CS35L45_BST_BPE_INST_L3_RLS_RATE_MASK,
CS35L45_BST_BPE_INST_L3_RLS_RATE_SHIFT},
[L4] = {"bst-bpe-inst-rls-rate", 0, 0, 0},
};
const struct of_entry bst_bpe_misc_map[BST_BPE_MISC_PARAMS] = {
[BST_BPE_INST_INF_HOLD_RLS] = {"bst-bpe-inst-inf-hold-rls",
CS35L45_BST_BPE_MISC_CONFIG,
CS35L45_BST_BPE_INST_INF_HOLD_RLS_MASK,
CS35L45_BST_BPE_INST_INF_HOLD_RLS_SHIFT},
[BST_BPE_IL_LIM_MODE] = {"bst-bpe-il-lim-mode",
CS35L45_BST_BPE_MISC_CONFIG,
CS35L45_BST_BPE_IL_LIM_MODE_MASK,
CS35L45_BST_BPE_IL_LIM_MODE_SHIFT},
[BST_BPE_OUT_OPMODE_SEL] = {"bst-bpe-out-opmode-sel",
CS35L45_BST_BPE_MISC_CONFIG,
CS35L45_BST_BPE_OUT_OPMODE_SEL_MASK,
CS35L45_BST_BPE_OUT_OPMODE_SEL_SHIFT},
[BST_BPE_INST_L3_BYP] = {"bst-bpe-inst-l3-byp",
CS35L45_BST_BPE_MISC_CONFIG,
CS35L45_BST_BPE_INST_L3_BYP_MASK,
CS35L45_BST_BPE_INST_L3_BYP_SHIFT},
[BST_BPE_INST_L2_BYP] = {"bst-bpe-inst-l2-byp",
CS35L45_BST_BPE_MISC_CONFIG,
CS35L45_BST_BPE_INST_L2_BYP_MASK,
CS35L45_BST_BPE_INST_L2_BYP_SHIFT},
[BST_BPE_INST_L1_BYP] = {"bst-bpe-inst-l1-byp",
CS35L45_BST_BPE_MISC_CONFIG,
CS35L45_BST_BPE_INST_L1_BYP_MASK,
CS35L45_BST_BPE_INST_L1_BYP_SHIFT},
[BST_BPE_FILT_SEL] = {"bst-bpe-filt-sel",
CS35L45_BST_BPE_MISC_CONFIG,
CS35L45_BST_BPE_FILT_SEL_MASK,
CS35L45_BST_BPE_FILT_SEL_SHIFT},
};
const struct of_entry bst_bpe_il_lim_map[BST_BPE_IL_LIM_PARAMS] = {
[BST_BPE_IL_LIM_THLD_DEL1] = {"bst-bpe-il-lim-thld-del1",
CS35L45_BST_BPE_IL_LIM_THLD,
CS35L45_BST_BPE_IL_LIM_THLD_DEL1_MASK,
CS35L45_BST_BPE_IL_LIM_THLD_DEL1_SHIFT},
[BST_BPE_IL_LIM_THLD_DEL2] = {"bst-bpe-il-lim-thld-del2",
CS35L45_BST_BPE_IL_LIM_THLD,
CS35L45_BST_BPE_IL_LIM_THLD_DEL2_MASK,
CS35L45_BST_BPE_IL_LIM_THLD_DEL2_SHIFT},
[BST_BPE_IL_LIM1_THLD] = {"bst-bpe-il-lim1-thld",
CS35L45_BST_BPE_IL_LIM_THLD,
CS35L45_BST_BPE_IL_LIM1_THLD_MASK,
CS35L45_BST_BPE_IL_LIM1_THLD_SHIFT},
[BST_BPE_IL_LIM1_DLY] = {"bst-bpe-il-lim1-dly",
CS35L45_BST_BPE_IL_LIM_DLY,
CS35L45_BST_BPE_IL_LIM1_DLY_MASK,
CS35L45_BST_BPE_IL_LIM1_DLY_SHIFT},
[BST_BPE_IL_LIM2_DLY] = {"bst-bpe-il-lim2-dly",
CS35L45_BST_BPE_IL_LIM_DLY,
CS35L45_BST_BPE_IL_LIM2_DLY_MASK,
CS35L45_BST_BPE_IL_LIM2_DLY_SHIFT},
[BST_BPE_IL_LIM_DLY_HYST] = {"bst-bpe-il-lim-dly-hyst",
CS35L45_BST_BPE_IL_LIM_DLY,
CS35L45_BST_BPE_IL_LIM_DLY_HYST_MASK,
CS35L45_BST_BPE_IL_LIM_DLY_HYST_SHIFT},
[BST_BPE_IL_LIM_THLD_HYST] = {"bst-bpe-il-lim-thld-hyst",
CS35L45_BST_BPE_IL_LIM_THLD,
CS35L45_BST_BPE_IL_LIM_THLD_HYST_MASK,
CS35L45_BST_BPE_IL_LIM_THLD_HYST_SHIFT},
[BST_BPE_IL_LIM1_ATK_RATE] = {"bst-bpe-il-lim1-atk-rate",
CS35L45_BST_BPE_IL_LIM_ATK_RATE,
CS35L45_BST_BPE_IL_LIM1_ATK_RATE_MASK,
CS35L45_BST_BPE_IL_LIM1_ATK_RATE_SHIFT},
[BST_BPE_IL_LIM2_ATK_RATE] = {"bst-bpe-il-lim2-atk-rate",
CS35L45_BST_BPE_IL_LIM_ATK_RATE,
CS35L45_BST_BPE_IL_LIM2_ATK_RATE_MASK,
CS35L45_BST_BPE_IL_LIM2_ATK_RATE_SHIFT},
[BST_BPE_IL_LIM1_RLS_RATE] = {"bst-bpe-il-lim1-rls-rate",
CS35L45_BST_BPE_IL_LIM_RLS_RATE,
CS35L45_BST_BPE_IL_LIM1_RLS_RATE_MASK,
CS35L45_BST_BPE_IL_LIM1_RLS_RATE_SHIFT},
[BST_BPE_IL_LIM2_RLS_RATE] = {"bst-bpe-il-lim2-rls-rate",
CS35L45_BST_BPE_IL_LIM_RLS_RATE,
CS35L45_BST_BPE_IL_LIM2_RLS_RATE_MASK,
CS35L45_BST_BPE_IL_LIM2_RLS_RATE_SHIFT},
};
const struct of_entry ldpm_map[LDPM_PARAMS] = {
[LDPM_GP1_BOOST_SEL] = {"ldpm-gp1-boost-sel", CS35L45_LDPM_CONFIG,
CS35L45_LDPM_GP1_BOOST_SEL_MASK,
CS35L45_LDPM_GP1_BOOST_SEL_SHIFT},
[LDPM_GP1_AMP_SEL] = {"ldpm-gp1-amp-sel", CS35L45_LDPM_CONFIG,
CS35L45_LDPM_GP1_AMP_SEL_MASK,
CS35L45_LDPM_GP1_AMP_SEL_SHIFT},
[LDPM_GP1_DELAY] = {"ldpm-gp1-delay", CS35L45_LDPM_CONFIG,
CS35L45_LDPM_GP1_DELAY_MASK,
CS35L45_LDPM_GP1_DELAY_SHIFT},
[LDPM_GP1_PCM_THLD] = {"ldpm-gp1-pcm-thld", CS35L45_LDPM_CONFIG,
CS35L45_LDPM_GP1_PCM_THLD_MASK,
CS35L45_LDPM_GP1_PCM_THLD_SHIFT},
[LDPM_GP2_IMON_SEL] = {"ldpm-gp2-imon-sel", CS35L45_LDPM_CONFIG,
CS35L45_LDPM_GP2_IMON_SEL_MASK,
CS35L45_LDPM_GP2_IMON_SEL_SHIFT},
[LDPM_GP2_VMON_SEL] = {"ldpm-gp2-vmon-sel", CS35L45_LDPM_CONFIG,
CS35L45_LDPM_GP2_VMON_SEL_MASK,
CS35L45_LDPM_GP2_VMON_SEL_SHIFT},
[LDPM_GP2_DELAY] = {"ldpm-gp2-delay", CS35L45_LDPM_CONFIG,
CS35L45_LDPM_GP2_DELAY_MASK,
CS35L45_LDPM_GP2_DELAY_SHIFT},
[LDPM_GP2_PCM_THLD] = {"ldpm-gp2-pcm-thld", CS35L45_LDPM_CONFIG,
CS35L45_LDPM_GP2_PCM_THLD_MASK,
CS35L45_LDPM_GP2_PCM_THLD_SHIFT},
};
const struct of_entry classh_map[CLASSH_PARAMS] = {
[CH_HDRM] = {"ch-hdrm", CS35L45_CLASSH_CONFIG1,
CS35L45_CH_HDRM_MASK, CS35L45_CH_HDRM_SHIFT},
[CH_RATIO] = {"ch-ratio", CS35L45_CLASSH_CONFIG1,
CS35L45_CH_RATIO_MASK, CS35L45_CH_RATIO_SHIFT},
[CH_REL_RATE] = {"ch-rel-rate", CS35L45_CLASSH_CONFIG1,
CS35L45_CH_REL_RATE_MASK, CS35L45_CH_REL_RATE_SHIFT},
[CH_OVB_THLD1] = {"ch-ovb-thld1", CS35L45_CLASSH_CONFIG2,
CS35L45_CH_OVB_THLD1_MASK, CS35L45_CH_OVB_THLD1_SHIFT},
[CH_OVB_THLDDELTA] = {"ch-ovb-thlddelta", CS35L45_CLASSH_CONFIG2,
CS35L45_CH_OVB_THLDDELTA_MASK, CS35L45_CH_OVB_THLDDELTA_SHIFT},
[CH_VDD_BST_MAX] = {"ch-vdd-bst-max", CS35L45_CLASSH_CONFIG2,
CS35L45_CH_VDD_BST_MAX_MASK, CS35L45_CH_VDD_BST_MAX_SHIFT},
[CH_OVB_RATIO] = {"ch-ovb-ratio", CS35L45_CLASSH_CONFIG3,
CS35L45_CH_OVB_RATIO_MASK, CS35L45_CH_OVB_RATIO_SHIFT},
[CH_THLD1_OFFSET] = {"ch-thld1-offset", CS35L45_CLASSH_CONFIG3,
CS35L45_CH_THLD1_OFFSET_MASK, CS35L45_CH_THLD1_OFFSET_SHIFT},
[AUD_MEM_DEPTH] = {"aud-mem-depth", CS35L45_AUD_MEM,
CS35L45_AUD_MEM_DEPTH_MASK, CS35L45_AUD_MEM_DEPTH_SHIFT},
};

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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
* cs35l45.h - CS35L45 ALSA SoC audio driver
*
* Copyright 2019 Cirrus Logic, Inc.
*
* Author: James Schulman <james.schulman@cirrus.com>
*
*/
#ifndef __CS35L45_H__
#define __CS35L45_H__
#include <linux/regmap.h>
#define CS35L45_DEVID 0x00000000
#define CS35L45_REVID 0x00000004
#define CS35L45_RELID 0x0000000C
#define CS35L45_OTPID 0x00000010
#define CS35L45_SFT_RESET 0x00000020
#define CS35L45_GLOBAL_ENABLES 0x00002014
#define CS35L45_BLOCK_ENABLES 0x00002018
#define CS35L45_BLOCK_ENABLES2 0x0000201C
#define CS35L45_GLOBAL_OVERRIDES 0x00002020
#define CS35L45_GLOBAL_SYNC 0x00002024
#define CS35L45_ERROR_RELEASE 0x00002034
#define CS35L45_CHIP_STATUS 0x00002040
#define CS35L45_REG_2114 0x00002114
#define CS35L45_REG_225C 0x0000225C
#define CS35L45_SYNC_GPIO1 0x00002430
#define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434
#define CS35L45_GPIO3 0x00002438
#define CS35L45_GPIO_GLOBAL_ENABLE_CONTROL 0x00002440
#define CS35L45_PWRMGT_CTL 0x00002900
#define CS35L45_WAKESRC_CTL 0x00002904
#define CS35L45_WKI2C_CTL 0x00002908
#define CS35L45_PWRMGT_STS 0x0000290C
#define CS35L45_REFCLK_INPUT 0x00002C04
#define CS35L45_REG_2C08 0x00002C08
#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C
#define CS35L45_SWIRE_CLK_CTRL 0x00002C14
#define CS35L45_SYNC_TX_RX_ENABLES 0x00003400
#define CS35L45_SYNC_SW_TX_ID 0x00003408
#define CS35L45_BOOST_VOLTAGE_CFG 0x00003800
#define CS35L45_BOOST_CCM_CFG 0x00003808
#define CS35L45_BOOST_DCM_CFG 0x0000380C
#define CS35L45_BOOST_LPMODE_CFG 0x00003810
#define CS35L45_BOOST_RAMP_CFG 0x00003814
#define CS35L45_BOOST_STARTUP_CFG 0x00003818
#define CS35L45_BOOST_OV_CFG 0x0000382C
#define CS35L45_BOOST_UV_CFG 0x00003830
#define CS35L45_BOOST_STATUS 0x00003834
#define CS35L45_BST_BPE_INST_THLD 0x00003C00
#define CS35L45_BST_BPE_INST_ILIM 0x00003C04
#define CS35L45_BST_BPE_INST_SS_ILIM 0x00003C08
#define CS35L45_BST_BPE_INST_ATK_RATE 0x00003C0C
#define CS35L45_BST_BPE_INST_HOLD_TIME 0x00003C10
#define CS35L45_BST_BPE_INST_RLS_RATE 0x00003C14
#define CS35L45_BST_BPE_MISC_CONFIG 0x00003C20
#define CS35L45_BST_BPE_IL_LIM_THLD 0x00003C24
#define CS35L45_BST_BPE_IL_LIM_DLY 0x00003C28
#define CS35L45_BST_BPE_IL_LIM_ATK_RATE 0x00003C2C
#define CS35L45_BST_BPE_IL_LIM_RLS_RATE 0x00003C30
#define CS35L45_BST_BPE_INST_STATUS 0x00003C3C
#define CS35L45_MONITOR_FILT 0x00004008
#define CS35L45_IMON_COMP 0x00004010
#define CS35L45_STATUS 0x00004200
#define CS35L45_MON_VALUE 0x00004404
#define CS35L45_ASP_ENABLES1 0x00004800
#define CS35L45_ASP_CONTROL1 0x00004804
#define CS35L45_ASP_CONTROL2 0x00004808
#define CS35L45_ASP_CONTROL3 0x0000480C
#define CS35L45_ASP_FRAME_CONTROL1 0x00004810
#define CS35L45_ASP_FRAME_CONTROL2 0x00004814
#define CS35L45_ASP_FRAME_CONTROL5 0x00004820
#define CS35L45_ASP_DATA_CONTROL1 0x00004830
#define CS35L45_ASP_DATA_CONTROL5 0x00004840
#define CS35L45_DACPCM1_INPUT 0x00004C00
#define CS35L45_MIXER_PILOT0_INPUT 0x00004C04
#define CS35L45_ASPTX1_INPUT 0x00004C20
#define CS35L45_ASPTX2_INPUT 0x00004C24
#define CS35L45_ASPTX3_INPUT 0x00004C28
#define CS35L45_ASPTX4_INPUT 0x00004C2C
#define CS35L45_ASPTX5_INPUT 0x00004C30
#define CS35L45_DSP1RX1_INPUT 0x00004C40
#define CS35L45_DSP1RX2_INPUT 0x00004C44
#define CS35L45_DSP1RX3_INPUT 0x00004C48
#define CS35L45_DSP1RX4_INPUT 0x00004C4C
#define CS35L45_DSP1RX5_INPUT 0x00004C50
#define CS35L45_DSP1RX6_INPUT 0x00004C54
#define CS35L45_DSP1RX7_INPUT 0x00004C58
#define CS35L45_DSP1RX8_INPUT 0x00004C5C
#define CS35L45_NGATE1_INPUT 0x00004C60
#define CS35L45_NGATE2_INPUT 0x00004C64
#define CS35L45_SWIRE_PORT1_CH1_INPUT 0x00004C70
#define CS35L45_SWIRE_PORT1_CH2_INPUT 0x00004C74
#define CS35L45_SWIRE_PORT1_CH3_INPUT 0x00004C78
#define CS35L45_SWIRE_PORT1_CH4_INPUT 0x00004C7C
#define CS35L45_SWIRE_PORT1_CH5_INPUT 0x00004C80
#define CS35L45_AMP_ERR_VOL_SEL 0x00006000
#define CS35L45_TEMP_WARN_THRESHOLD 0x00006020
#define CS35L45_TEMP_WARN_CONFIG 0x00006024
#define CS35L45_TEMP_WARN_TRIG_AUTO 0x00006028
#define CS35L45_TEMP_WARN_STATUS 0x0000602C
#define CS35L45_BPE_INST_THLD 0x00006064
#define CS35L45_BPE_INST_ATTN 0x00006068
#define CS35L45_BPE_INST_ATK_RATE 0x00006074
#define CS35L45_BPE_INST_HOLD_TIME 0x00006080
#define CS35L45_BPE_INST_RLS_RATE 0x00006084
#define CS35L45_BPE_MISC_CONFIG 0x00006090
#define CS35L45_BPE_INST_STATUS 0x00006094
#define CS35L45_HVLV_CONFIG 0x00006400
#define CS35L45_LDPM_CONFIG 0x00006404
#define CS35L45_CLASSH_CONFIG1 0x00006408
#define CS35L45_CLASSH_CONFIG2 0x0000640C
#define CS35L45_CLASSH_CONFIG3 0x00006410
#define CS35L45_AUD_MEM 0x00006418
#define CS35L45_AMP_PCM_CONTROL 0x00007000
#define CS35L45_AMP_PCM_HPF_TST 0x00007004
#define CS35L45_AMP_GAIN 0x00007800
#define CS35L45_DAC_MSM_CONFIG 0x00007C00
#define CS35L45_AMP_OUTPUT_MUTE 0x00007C04
#define CS35L45_AMP_OUTPUT_DRV 0x00007C08
#define CS35L45_ALIVE_DCIN_WD 0x00007C20
#define CS35L45_IRQ1_CFG 0x0000E000
#define CS35L45_IRQ1_STATUS 0x0000E004
#define CS35L45_IRQ1_EINT_1 0x0000E010
#define CS35L45_IRQ1_EINT_2 0x0000E014
#define CS35L45_IRQ1_EINT_3 0x0000E018
#define CS35L45_IRQ1_EINT_4 0x0000E01C
#define CS35L45_IRQ1_EINT_5 0x0000E020
#define CS35L45_IRQ1_EINT_7 0x0000E028
#define CS35L45_IRQ1_EINT_8 0x0000E02C
#define CS35L45_IRQ1_EINT_18 0x0000E054
#define CS35L45_IRQ1_STS_1 0x0000E090
#define CS35L45_IRQ1_STS_2 0x0000E094
#define CS35L45_IRQ1_STS_3 0x0000E098
#define CS35L45_IRQ1_STS_4 0x0000E09C
#define CS35L45_IRQ1_STS_5 0x0000E0A0
#define CS35L45_IRQ1_STS_7 0x0000E0A8
#define CS35L45_IRQ1_STS_8 0x0000E0AC
#define CS35L45_IRQ1_STS_18 0x0000E0D4
#define CS35L45_IRQ1_MASK_1 0x0000E110
#define CS35L45_IRQ1_MASK_2 0x0000E114
#define CS35L45_IRQ1_MASK_3 0x0000E118
#define CS35L45_IRQ1_MASK_4 0x0000E11C
#define CS35L45_IRQ1_MASK_5 0x0000E120
#define CS35L45_IRQ1_MASK_7 0x0000E128
#define CS35L45_IRQ1_MASK_8 0x0000E12C
#define CS35L45_IRQ1_MASK_18 0x0000E154
#define CS35L45_IRQ1_EDGE_1 0x0000E210
#define CS35L45_IRQ1_EDGE_4 0x0000E21C
#define CS35L45_IRQ1_POL_1 0x0000E290
#define CS35L45_IRQ1_POL_2 0x0000E294
#define CS35L45_IRQ1_POL_4 0x0000E29C
#define CS35L45_IRQ1_DB_3 0x0000E318
#define CS35L45_IRQ2_CFG 0x0000E800
#define CS35L45_IRQ2_STATUS 0x0000E804
#define CS35L45_IRQ2_EINT_1 0x0000E810
#define CS35L45_IRQ2_EINT_2 0x0000E814
#define CS35L45_IRQ2_EINT_3 0x0000E818
#define CS35L45_IRQ2_EINT_4 0x0000E81C
#define CS35L45_IRQ2_EINT_5 0x0000E820
#define CS35L45_IRQ2_EINT_7 0x0000E828
#define CS35L45_IRQ2_EINT_8 0x0000E82C
#define CS35L45_IRQ2_EINT_18 0x0000E854
#define CS35L45_IRQ2_STS_1 0x0000E890
#define CS35L45_IRQ2_STS_2 0x0000E894
#define CS35L45_IRQ2_STS_3 0x0000E898
#define CS35L45_IRQ2_STS_4 0x0000E89C
#define CS35L45_IRQ2_STS_5 0x0000E8A0
#define CS35L45_IRQ2_STS_7 0x0000E8A8
#define CS35L45_IRQ2_STS_8 0x0000E8AC
#define CS35L45_IRQ2_STS_18 0x0000E8D4
#define CS35L45_IRQ2_MASK_1 0x0000E910
#define CS35L45_IRQ2_MASK_2 0x0000E914
#define CS35L45_IRQ2_MASK_3 0x0000E918
#define CS35L45_IRQ2_MASK_4 0x0000E91C
#define CS35L45_IRQ2_MASK_5 0x0000E920
#define CS35L45_IRQ2_MASK_7 0x0000E928
#define CS35L45_IRQ2_MASK_8 0x0000E92C
#define CS35L45_IRQ2_MASK_18 0x0000E954
#define CS35L45_IRQ2_EDGE_1 0x0000EA10
#define CS35L45_IRQ2_EDGE_4 0x0000EA1C
#define CS35L45_IRQ2_POL_1 0x0000EA90
#define CS35L45_IRQ2_POL_2 0x0000EA94
#define CS35L45_IRQ2_POL_4 0x0000EA9C
#define CS35L45_IRQ2_DB_3 0x0000EB18
#define CS35L45_GPIO_STATUS1 0x0000F000
#define CS35L45_GPIO1_CTRL1 0x0000F008
#define CS35L45_GPIO2_CTRL1 0x0000F00C
#define CS35L45_GPIO3_CTRL1 0x0000F010
#define CS35L45_MIXER_NGATE_CH1_CFG 0x00010004
#define CS35L45_MIXER_NGATE_CH2_CFG 0x00010008
#define CS35L45_DSP_MBOX_1 0x00011000
#define CS35L45_DSP_MBOX_2 0x00011004
#define CS35L45_DSP_MBOX_3 0x00011008
#define CS35L45_DSP_MBOX_4 0x0001100C
#define CS35L45_DSP_MBOX_5 0x00011010
#define CS35L45_DSP_MBOX_6 0x00011014
#define CS35L45_DSP_MBOX_7 0x00011018
#define CS35L45_DSP_MBOX_8 0x0001101C
#define CS35L45_DSP_VIRT1_MBOX_1 0x00011020
#define CS35L45_DSP_VIRT1_MBOX_2 0x00011024
#define CS35L45_DSP_VIRT1_MBOX_3 0x00011028
#define CS35L45_DSP_VIRT1_MBOX_4 0x0001102C
#define CS35L45_DSP_VIRT1_MBOX_5 0x00011030
#define CS35L45_DSP_VIRT1_MBOX_6 0x00011034
#define CS35L45_DSP_VIRT1_MBOX_7 0x00011038
#define CS35L45_DSP_VIRT1_MBOX_8 0x0001103C
#define CS35L45_DSP_VIRT2_MBOX_1 0x00011040
#define CS35L45_DSP_VIRT2_MBOX_2 0x00011044
#define CS35L45_DSP_VIRT2_MBOX_3 0x00011048
#define CS35L45_DSP_VIRT2_MBOX_4 0x0001104C
#define CS35L45_DSP_VIRT2_MBOX_5 0x00011050
#define CS35L45_DSP_VIRT2_MBOX_6 0x00011054
#define CS35L45_DSP_VIRT2_MBOX_7 0x00011058
#define CS35L45_DSP_VIRT2_MBOX_8 0x0001105C
#define CS35L45_CLOCK_DETECT_1 0x00012000
#define CS35L45_DSP1_XMEM_PACK_0 0x02000000
#define CS35L45_DSP1_XMEM_PACK_4607 0x020047FC
#define CS35L45_DSP1_XMEM_UNPACK32_0 0x02400000
#define CS35L45_DSP1_XMEM_UNPACK32_3071 0x02402FFC
#define CS35L45_DSP1_SYS_ID 0x025E0000
#define CS35L45_DSP1_XMEM_UNPACK24_0 0x02800000
#define CS35L45_DSP1_XMEM_UNPACK24_6143 0x02805FFC
#define CS35L45_DSP1_CLOCK_FREQ 0x02B80000
#define CS35L45_DSP1_RX1_RATE 0x02B80080
#define CS35L45_DSP1_RX2_RATE 0x02B80088
#define CS35L45_DSP1_RX3_RATE 0x02B80090
#define CS35L45_DSP1_RX4_RATE 0x02B80098
#define CS35L45_DSP1_RX5_RATE 0x02B800A0
#define CS35L45_DSP1_RX6_RATE 0x02B800A8
#define CS35L45_DSP1_RX7_RATE 0x02B800B0
#define CS35L45_DSP1_RX8_RATE 0x02B800B8
#define CS35L45_DSP1_TX1_RATE 0x02B80280
#define CS35L45_DSP1_TX2_RATE 0x02B80288
#define CS35L45_DSP1_TX3_RATE 0x02B80290
#define CS35L45_DSP1_TX4_RATE 0x02B80298
#define CS35L45_DSP1_TX5_RATE 0x02B802A0
#define CS35L45_DSP1_TX6_RATE 0x02B802A8
#define CS35L45_DSP1_TX7_RATE 0x02B802B0
#define CS35L45_DSP1_TX8_RATE 0x02B802B8
#define CS35L45_DSP1_SCRATCH1 0x02B805C0
#define CS35L45_DSP1_SCRATCH2 0x02B805C8
#define CS35L45_DSP1_SCRATCH3 0x02B805D0
#define CS35L45_DSP1_SCRATCH4 0x02B805D8
#define CS35L45_DSP1_CCM_CORE_CONTROL 0x02BC1000
#define CS35L45_DSP1_STREAM_ARB_MSTR1_CONFIG_0 0x02BC5000
#define CS35L45_DSP1_STREAM_ARB_TX1_CONFIG_0 0x02BC5200
#define CS35L45_DSP1_YMEM_PACK_0 0x02C00000
#define CS35L45_DSP1_YMEM_PACK_1532 0x02C017F0
#define CS35L45_DSP1_YMEM_UNPACK32_0 0x03000000
#define CS35L45_DSP1_YMEM_UNPACK32_1022 0x03000FF8
#define CS35L45_DSP1_YMEM_UNPACK24_0 0x03400000
#define CS35L45_DSP1_YMEM_UNPACK24_2043 0x03401FEC
#define CS35L45_DSP1_PMEM_0 0x03800000
#define CS35L45_DSP1_PMEM_3834 0x03803BE8
#define CS35L45_LASTREG 0x03C6EFE8
#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000
#define CS35L45_GLOBAL_EN_SHIFT 0
#define CS35L45_GLOBAL_EN_MASK BIT(0)
#define CS35L45_TEMPMON_GLOBAL_OVR_SHIFT 3
#define CS35L45_TEMPMON_GLOBAL_OVR_MASK BIT(3)
#define CS35L45_BST_DISABLE_FET_OFF 0x00
#define CS35L45_BST_DISABLE_FET_ON 0x01
#define CS35L45_BST_ENABLE 0x02
#define CS35L45_BST_EN_SHIFT 4
#define CS35L45_BST_EN_MASK GENMASK(5, 4)
#define CS35L45_AMP_DRE_EN_SHIFT 20
#define CS35L45_AMP_DRE_EN_MASK BIT(20)
#define CS35L45_SYNC_EN_SHIFT 8
#define CS35L45_SYNC_EN_MASK BIT(8)
#define CS35L45_MEM_RDY_SHIFT 1
#define CS35L45_MEM_RDY_MASK BIT(1)
#define CS35L45_WKSRC_SYNC_GPIO1 BIT(0)
#define CS35L45_WKSRC_INT_GPIO2 BIT(1)
#define CS35L45_WKSRC_GPIO3 BIT(2)
#define CS35L45_WKSRC_SPI BIT(3)
#define CS35L45_WKSRC_I2C BIT(4)
#define CS35L45_UPDT_WKCTL_SHIFT 15
#define CS35L45_UPDT_WKCTL_MASK BIT(15)
#define CS35L45_WKSRC_EN_SHIFT 8
#define CS35L45_WKSRC_EN_MASK GENMASK(12, 8)
#define CS35L45_WKSRC_POL_SHIFT 0
#define CS35L45_WKSRC_POL_MASK GENMASK(3, 0)
#define CS35L45_UPDT_WKI2C_SHIFT 15
#define CS35L45_UPDT_WKI2C_MASK BIT(15)
#define CS35L45_WKI2C_ADDR_SHIFT 0
#define CS35L45_WKI2C_ADDR_MASK GENMASK(6, 0)
#define CS35L45_CCM_CORE_RESET_SHIFT 9
#define CS35L45_CCM_CORE_RESET_MASK BIT(9)
#define CS35L45_CCM_PM_REMAP_SHIFT 7
#define CS35L45_CCM_PM_REMAP_MASK BIT(7)
#define CS35L45_CCM_CORE_EN_SHIFT 0
#define CS35L45_CCM_CORE_EN_MASK BIT(0)
#define CS35L45_DSP1_STREAM_ARB_MSTR0_EN_SHIFT 0
#define CS35L45_DSP1_STREAM_ARB_MSTR0_EN_MASK BIT(0)
#define CS35L45_DSP1_STREAM_ARB_TX1_EN_SHIFT 0
#define CS35L45_DSP1_STREAM_ARB_TX1_EN_MASK BIT(0)
#define CS35L45_DSP_N_RX_RATES 8
#define CS35L45_DSP_N_TX_RATES 8
#define CS35L45_DSP_RATE_SHIFT 0
#define CS35L45_DSP_RATE_MASK 0x1f
#define CS35L45_DSP_SAMPLE_RATE_RX1 0x00080
#define CS35L45_DSP_SAMPLE_RATE_TX1 0x00280
#define CS35L45_48P0_KHZ 0x03
#define CS35L45_96P0_KHZ 0x04
#define CS35L45_44P100_KHZ 0x0B
#define CS35L45_88P200_KHZ 0x0C
#define CS35L45_8_KHZ 0x11
#define CS35L45_16_KHZ 0x12
#define CS35L45_GLOBAL_FS_SHIFT 0
#define CS35L45_GLOBAL_FS_MASK GENMASK(4, 0)
#define CS35L45_SYNC_LSW_RX_EN_SHIFT 19
#define CS35L45_SYNC_LSW_RX_EN_MASK BIT(19)
#define CS35L45_SYNC_LSW_TX_EN_SHIFT 18
#define CS35L45_SYNC_LSW_TX_EN_MASK BIT(18)
#define CS35L45_SYNC_SW_RX_EN_SHIFT 17
#define CS35L45_SYNC_SW_RX_EN_MASK BIT(17)
#define CS35L45_SYNC_SW_TX_EN_SHIFT 16
#define CS35L45_SYNC_SW_TX_EN_MASK BIT(16)
#define CS35L45_SYNC_PWR_RX_EN_SHIFT 5
#define CS35L45_SYNC_PWR_RX_EN_MASK BIT(5)
#define CS35L45_SYNC_PWR_TX_EN_SHIFT 4
#define CS35L45_SYNC_PWR_TX_EN_MASK BIT(4)
#define CS35L45_SYNC_SW_EN_MASK (CS35L45_SYNC_LSW_RX_EN_MASK | \
CS35L45_SYNC_LSW_TX_EN_MASK | \
CS35L45_SYNC_SW_RX_EN_MASK | \
CS35L45_SYNC_SW_TX_EN_MASK)
#define CS35L45_SYNC_LSW_TXID_SHIFT 8
#define CS35L45_SYNC_LSW_TXID_MASK GENMASK(10, 8)
#define CS35L45_SYNC_SW_TXID_SHIFT 0
#define CS35L45_SYNC_SW_TXID_MASK GENMASK(2, 0)
#define CS35L45_PLL_REFCLK_SEL_BCLK 0x0
#define CS35L45_PLL_REFCLK_SEL_SWIRE_CLK 0x7
#define CS35L45_PLL_FORCE_EN_SHIFT 16
#define CS35L45_PLL_FORCE_EN_MASK BIT(16)
#define CS35L45_PLL_OPEN_LOOP_SHIFT 11
#define CS35L45_PLL_OPEN_LOOP_MASK BIT(11)
#define CS35L45_PLL_REFCLK_FREQ_SHIFT 5
#define CS35L45_PLL_REFCLK_FREQ_MASK GENMASK(10, 5)
#define CS35L45_PLL_REFCLK_EN_SHIFT 4
#define CS35L45_PLL_REFCLK_EN_MASK BIT(4)
#define CS35L45_PLL_REFCLK_SEL_SHIFT 0
#define CS35L45_PLL_REFCLK_SEL_MASK GENMASK(2, 0)
#define CS35L45_BST_BPE_INST_L3_THLD_SHIFT 24
#define CS35L45_BST_BPE_INST_L3_THLD_MASK GENMASK(31, 24)
#define CS35L45_BST_BPE_INST_L2_THLD_SHIFT 16
#define CS35L45_BST_BPE_INST_L2_THLD_MASK GENMASK(23, 16)
#define CS35L45_BST_BPE_INST_L1_THLD_SHIFT 8
#define CS35L45_BST_BPE_INST_L1_THLD_MASK GENMASK(15, 8)
#define CS35L45_BST_BPE_INST_L0_THLD_SHIFT 0
#define CS35L45_BST_BPE_INST_L0_THLD_MASK GENMASK(7, 0)
#define CS35L45_BST_BPE_INST_L4_ILIM_SHIFT 24
#define CS35L45_BST_BPE_INST_L4_ILIM_MASK GENMASK(30, 24)
#define CS35L45_BST_BPE_INST_L3_ILIM_SHIFT 16
#define CS35L45_BST_BPE_INST_L3_ILIM_MASK GENMASK(22, 16)
#define CS35L45_BST_BPE_INST_L2_ILIM_SHIFT 8
#define CS35L45_BST_BPE_INST_L2_ILIM_MASK GENMASK(14, 8)
#define CS35L45_BST_BPE_INST_L1_ILIM_SHIFT 0
#define CS35L45_BST_BPE_INST_L1_ILIM_MASK GENMASK(6, 0)
#define CS35L45_BST_BPE_INST_L4_SS_ILIM_SHIFT 24
#define CS35L45_BST_BPE_INST_L4_SS_ILIM_MASK GENMASK(30, 24)
#define CS35L45_BST_BPE_INST_L3_SS_ILIM_SHIFT 16
#define CS35L45_BST_BPE_INST_L3_SS_ILIM_MASK GENMASK(22, 16)
#define CS35L45_BST_BPE_INST_L2_SS_ILIM_SHIFT 8
#define CS35L45_BST_BPE_INST_L2_SS_ILIM_MASK GENMASK(14, 8)
#define CS35L45_BST_BPE_INST_L1_SS_ILIM_SHIFT 0
#define CS35L45_BST_BPE_INST_L1_SS_ILIM_MASK GENMASK(6, 0)
#define CS35L45_BST_BPE_INST_L3_ATK_RATE_SHIFT 24
#define CS35L45_BST_BPE_INST_L3_ATK_RATE_MASK GENMASK(26, 24)
#define CS35L45_BST_BPE_INST_L2_ATK_RATE_SHIFT 16
#define CS35L45_BST_BPE_INST_L2_ATK_RATE_MASK GENMASK(18, 16)
#define CS35L45_BST_BPE_INST_L1_ATK_RATE_SHIFT 8
#define CS35L45_BST_BPE_INST_L1_ATK_RATE_MASK GENMASK(10, 8)
#define CS35L45_BST_BPE_INST_L3_HOLD_TIME_SHIFT 24
#define CS35L45_BST_BPE_INST_L3_HOLD_TIME_MASK GENMASK(27, 24)
#define CS35L45_BST_BPE_INST_L2_HOLD_TIME_SHIFT 16
#define CS35L45_BST_BPE_INST_L2_HOLD_TIME_MASK GENMASK(19, 16)
#define CS35L45_BST_BPE_INST_L1_HOLD_TIME_SHIFT 8
#define CS35L45_BST_BPE_INST_L1_HOLD_TIME_MASK GENMASK(11, 8)
#define CS35L45_BST_BPE_INST_L0_HOLD_TIME_SHIFT 0
#define CS35L45_BST_BPE_INST_L0_HOLD_TIME_MASK GENMASK(3, 0)
#define CS35L45_BST_BPE_INST_L3_RLS_RATE_SHIFT 24
#define CS35L45_BST_BPE_INST_L3_RLS_RATE_MASK GENMASK(28, 24)
#define CS35L45_BST_BPE_INST_L2_RLS_RATE_SHIFT 16
#define CS35L45_BST_BPE_INST_L2_RLS_RATE_MASK GENMASK(20, 16)
#define CS35L45_BST_BPE_INST_L1_RLS_RATE_SHIFT 8
#define CS35L45_BST_BPE_INST_L1_RLS_RATE_MASK GENMASK(12, 8)
#define CS35L45_BST_BPE_INST_L0_RLS_RATE_SHIFT 0
#define CS35L45_BST_BPE_INST_L0_RLS_RATE_MASK GENMASK(4, 0)
#define CS35L45_BST_BPE_INST_INF_HOLD_RLS_SHIFT 16
#define CS35L45_BST_BPE_INST_INF_HOLD_RLS_MASK BIT(16)
#define CS35L45_BST_BPE_IL_LIM_MODE_SHIFT 15
#define CS35L45_BST_BPE_IL_LIM_MODE_MASK BIT(15)
#define CS35L45_BST_BPE_OUT_OPMODE_SEL_SHIFT 12
#define CS35L45_BST_BPE_OUT_OPMODE_SEL_MASK GENMASK(13, 12)
#define CS35L45_BST_BPE_INST_L3_BYP_SHIFT 10
#define CS35L45_BST_BPE_INST_L3_BYP_MASK BIT(10)
#define CS35L45_BST_BPE_INST_L2_BYP_SHIFT 9
#define CS35L45_BST_BPE_INST_L2_BYP_MASK BIT(9)
#define CS35L45_BST_BPE_INST_L1_BYP_SHIFT 8
#define CS35L45_BST_BPE_INST_L1_BYP_MASK BIT(8)
#define CS35L45_BST_BPE_FILT_SEL_SHIFT 0
#define CS35L45_BST_BPE_FILT_SEL_MASK GENMASK(1, 0)
#define CS35L45_BST_BPE_IL_LIM_THLD_HYST_SHIFT 24
#define CS35L45_BST_BPE_IL_LIM_THLD_HYST_MASK GENMASK(28, 24)
#define CS35L45_BST_BPE_IL_LIM_THLD_DEL2_SHIFT 16
#define CS35L45_BST_BPE_IL_LIM_THLD_DEL2_MASK GENMASK(23, 16)
#define CS35L45_BST_BPE_IL_LIM_THLD_DEL1_SHIFT 8
#define CS35L45_BST_BPE_IL_LIM_THLD_DEL1_MASK GENMASK(15, 8)
#define CS35L45_BST_BPE_IL_LIM1_THLD_SHIFT 0
#define CS35L45_BST_BPE_IL_LIM1_THLD_MASK GENMASK(7, 0)
#define CS35L45_BST_BPE_IL_LIM_DLY_HYST_SHIFT 16
#define CS35L45_BST_BPE_IL_LIM_DLY_HYST_MASK GENMASK(22, 16)
#define CS35L45_BST_BPE_IL_LIM2_DLY_SHIFT 8
#define CS35L45_BST_BPE_IL_LIM2_DLY_MASK GENMASK(15, 8)
#define CS35L45_BST_BPE_IL_LIM1_DLY_SHIFT 0
#define CS35L45_BST_BPE_IL_LIM1_DLY_MASK GENMASK(7, 0)
#define CS35L45_BST_BPE_IL_LIM2_ATK_RATE_SHIFT 8
#define CS35L45_BST_BPE_IL_LIM2_ATK_RATE_MASK GENMASK(10, 8)
#define CS35L45_BST_BPE_IL_LIM1_ATK_RATE_SHIFT 0
#define CS35L45_BST_BPE_IL_LIM1_ATK_RATE_MASK GENMASK(2, 0)
#define CS35L45_BST_BPE_IL_LIM2_RLS_RATE_SHIFT 8
#define CS35L45_BST_BPE_IL_LIM2_RLS_RATE_MASK GENMASK(12, 8)
#define CS35L45_BST_BPE_IL_LIM1_RLS_RATE_SHIFT 0
#define CS35L45_BST_BPE_IL_LIM1_RLS_RATE_MASK GENMASK(4, 0)
#define CS35L45_ASP_WIDTH_16 0x10
#define CS35L45_ASP_WIDTH_24 0x18
#define CS35L45_ASP_WIDTH_32 0x20
#define CS35L45_ASP_WIDTH_RX_SHIFT 24
#define CS35L45_ASP_WIDTH_RX_MASK GENMASK(31, 24)
#define CS35L45_ASP_WIDTH_TX_SHIFT 16
#define CS35L45_ASP_WIDTH_TX_MASK GENMASK(23, 16)
#define CS35L45_ASP_FMT_SHIFT 8
#define CS35L45_ASP_FMT_MASK GENMASK(10, 8)
#define CS35L45_ASP_BCLK_INV_SHIFT 6
#define CS35L45_ASP_BCLK_INV_MASK BIT(6)
#define CS35L45_ASP_BCLK_MSTR_SHIFT 4
#define CS35L45_ASP_BCLK_MSTR_MASK BIT(4)
#define CS35L45_ASP_FSYNC_INV_SHIFT 2
#define CS35L45_ASP_FSYNC_INV_MASK BIT(2)
#define CS35L45_ASP_FSYNC_MSTR_SHIFT 0
#define CS35L45_ASP_FSYNC_MSTR_MASK BIT(0)
#define CS35L45_ASP_WL_MAX 24
#define CS35L45_ASP_WL_MIN 12
#define CS35L45_ASP_WL_SHIFT 0
#define CS35L45_ASP_WL_MASK GENMASK(5, 0)
#define CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT 0
#define CS35L45_ASP_DOUT_HIZ_CTRL_MASK GENMASK(1, 0)
#define CS35L45_ASP_TX4_SLOT_SHIFT 24
#define CS35L45_ASP_TX4_SLOT_MASK GENMASK(29, 24)
#define CS35L45_ASP_TX3_SLOT_SHIFT 16
#define CS35L45_ASP_TX3_SLOT_MASK GENMASK(21, 16)
#define CS35L45_ASP_TX2_SLOT_SHIFT 8
#define CS35L45_ASP_TX2_SLOT_MASK GENMASK(13, 8)
#define CS35L45_ASP_TX1_SLOT_SHIFT 0
#define CS35L45_ASP_TX1_SLOT_MASK GENMASK(5, 0)
#define CS35L45_ASP_TX_ALL_SLOTS (CS35L45_ASP_TX4_SLOT_MASK | \
CS35L45_ASP_TX3_SLOT_MASK | \
CS35L45_ASP_TX2_SLOT_MASK | \
CS35L45_ASP_TX1_SLOT_MASK)
#define CS35L45_ASP_RX2_SLOT_SHIFT 8
#define CS35L45_ASP_RX2_SLOT_MASK GENMASK(13, 8)
#define CS35L45_ASP_RX1_SLOT_SHIFT 0
#define CS35L45_ASP_RX1_SLOT_MASK GENMASK(5, 0)
#define CS35L45_ASP_RX_ALL_SLOTS (CS35L45_ASP_RX2_SLOT_MASK | \
CS35L45_ASP_RX1_SLOT_MASK)
#define CS35L45_PCM_SRC_MASK 0x7F
#define CS35L45_PCM_SRC_ZERO 0x00
#define CS35L45_PCM_SRC_ASP_RX1 0x08
#define CS35L45_PCM_SRC_ASP_RX2 0x09
#define CS35L45_PCM_SRC_VMON 0x18
#define CS35L45_PCM_SRC_IMON 0x19
#define CS35L45_PCM_SRC_ERR_VOL 0x20
#define CS35L45_PCM_SRC_CLASSH_TGT 0x21
#define CS35L45_PCM_SRC_VDD_BATTMON 0x28
#define CS35L45_PCM_SRC_VDD_BSTMON 0x29
#define CS35L45_PCM_SRC_DSP_TX1 0x32
#define CS35L45_PCM_SRC_DSP_TX2 0x33
#define CS35L45_PCM_SRC_TEMPMON 0x3A
#define CS35L45_PCM_SRC_SWIRE_RX1 0x44
#define CS35L45_PCM_SRC_SWIRE_RX2 0x45
#define CS35L45_FORCE_LV_OPERATION 0x01
#define CS35L45_FORCE_HV_OPERATION 0x02
#define CS35L45_HVLV_OPERATION 0x03
#define CS35L45_HVLV_THLD_HYS_SHIFT 22
#define CS35L45_HVLV_THLD_HYS_MASK GENMASK(23, 22)
#define CS35L45_HVLV_THLD_SHIFT 16
#define CS35L45_HVLV_THLD_MASK GENMASK(20, 16)
#define CS35L45_HVLV_DLY_SHIFT 2
#define CS35L45_HVLV_DLY_MASK GENMASK(4, 2)
#define CS35L45_HVLV_MODE_SHIFT 0
#define CS35L45_HVLV_MODE_MASK GENMASK(1, 0)
#define CS35L45_LDPM_GP1_BOOST_SEL_SHIFT 15
#define CS35L45_LDPM_GP1_BOOST_SEL_MASK BIT(15)
#define CS35L45_LDPM_GP1_AMP_SEL_SHIFT 14
#define CS35L45_LDPM_GP1_AMP_SEL_MASK BIT(14)
#define CS35L45_LDPM_GP1_DELAY_SHIFT 11
#define CS35L45_LDPM_GP1_DELAY_MASK GENMASK(13, 11)
#define CS35L45_LDPM_GP1_PCM_THLD_SHIFT 8
#define CS35L45_LDPM_GP1_PCM_THLD_MASK GENMASK(10, 8)
#define CS35L45_LDPM_GP2_IMON_SEL_SHIFT 7
#define CS35L45_LDPM_GP2_IMON_SEL_MASK BIT(7)
#define CS35L45_LDPM_GP2_VMON_SEL_SHIFT 6
#define CS35L45_LDPM_GP2_VMON_SEL_MASK BIT(6)
#define CS35L45_LDPM_GP2_DELAY_SHIFT 3
#define CS35L45_LDPM_GP2_DELAY_MASK GENMASK(5, 3)
#define CS35L45_LDPM_GP2_PCM_THLD_SHIFT 0
#define CS35L45_LDPM_GP2_PCM_THLD_MASK GENMASK(2, 0)
#define CS35L45_CH_HDRM_SHIFT 24
#define CS35L45_CH_HDRM_MASK GENMASK(30, 24)
#define CS35L45_CH_RATIO_SHIFT 8
#define CS35L45_CH_RATIO_MASK GENMASK(12, 8)
#define CS35L45_CH_REL_RATE_SHIFT 0
#define CS35L45_CH_REL_RATE_MASK GENMASK(7, 0)
#define CS35L45_CH_OVB_THLD1_SHIFT 16
#define CS35L45_CH_OVB_THLD1_MASK GENMASK(23, 16)
#define CS35L45_CH_OVB_THLDDELTA_SHIFT 8
#define CS35L45_CH_OVB_THLDDELTA_MASK GENMASK(15, 8)
#define CS35L45_CH_VDD_BST_MAX_SHIFT 0
#define CS35L45_CH_VDD_BST_MAX_MASK GENMASK(7, 0)
#define CS35L45_CH_OVB_LATCH_SHIFT 31
#define CS35L45_CH_OVB_LATCH_MASK BIT(31)
#define CS35L45_CH_OVB_RATIO_SHIFT 16
#define CS35L45_CH_OVB_RATIO_MASK GENMASK(20, 16)
#define CS35L45_CH_THLD1_OFFSET_SHIFT 0
#define CS35L45_CH_THLD1_OFFSET_MASK GENMASK(11, 0)
#define CS35L45_AUD_MEM_DEPTH_SHIFT 0
#define CS35L45_AUD_MEM_DEPTH_MASK GENMASK(2, 0)
#define CS35l45_HPF_DEFAULT 0x00000000
#define CS35L45_HPF_44P1 0x000108BD
#define CS35L45_HPF_88P2 0x0001045F
#define CS35L45_AMP_VOL_PCM_MUTE 0x04CF
#define CS35L45_AMP_VOL_PCM_SHIFT 0
#define CS35L45_AMP_VOL_PCM_MASK GENMASK(10, 0)
#define CS35L45_AMP_GAIN_PCM_10DBV 0x00
#define CS35L45_AMP_GAIN_PCM_13DBV 0x01
#define CS35L45_AMP_GAIN_PCM_16DBV 0x02
#define CS35L45_AMP_GAIN_PCM_19DBV 0x03
#define CS35L45_AMP_GAIN_PCM_SHIFT 8
#define CS35L45_AMP_GAIN_PCM_MASK GENMASK(9, 8)
#define CS35L45_AMP_MUTE_SHIFT 0
#define CS35L45_AMP_MUTE_MASK BIT(0)
#define CS35L45_AMP_SHORT_ERR_MASK BIT(31)
#define CS35L45_BST_SHORT_ERR_MASK BIT(8)
#define CS35L45_MSM_PUP_DONE_MASK BIT(24)
#define CS35L45_MSM_PDN_DONE_MASK BIT(23)
#define CS35L45_MSM_GLOBAL_EN_ASSERT_MASK BIT(22)
#define CS35L45_DSP_VIRT1_MBOX_MASK BIT(20)
#define CS35L45_DSP_VIRT2_MBOX_MASK BIT(21)
#define CS35L45_PLL_UNLOCK_FLAG_RISE_MASK BIT(4)
#define CS35L45_PLL_LOCK_FLAG_MASK BIT(1)
#define CS35L45_OTP_BOOT_DONE_STS_MASK BIT(1)
#define CS35L45_OTP_BUSY_MASK BIT(0)
#define CS35L45_GLOBAL_ERROR_MASK BIT(15)
#define CS35L45_GPIO_DIR_SHIFT 31
#define CS35L45_GPIO_DIR_MASK BIT(31)
#define CS35L45_GPIO_LVL_SHIFT 15
#define CS35L45_GPIO_LVL_MASK BIT(15)
#define CS35L45_GPIO_OP_CFG_SHIFT 14
#define CS35L45_GPIO_OP_CFG_MASK BIT(14)
#define CS35L45_GPIO_POL_SHIFT 12
#define CS35L45_GPIO_POL_MASK BIT(12)
#define CS35L45_GPIO_CTRL_SHIFT 20
#define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20)
#define CS35L45_GPIO_INVERT_SHIFT 19
#define CS35L45_GPIO_INVERT_MASK BIT(19)
#define CS35L45_AUX_NGATE_CH_EN_SHIFT 16
#define CS35L45_AUX_NGATE_CH_EN_MASK BIT(16)
#define CS35L45_AUX_NGATE_CH_HOLD_SHIFT 8
#define CS35L45_AUX_NGATE_CH_HOLD_MASK GENMASK(11, 8)
#define CS35L45_AUX_NGATE_CH_THR_SHIFT 0
#define CS35L45_AUX_NGATE_CH_THR_MASK GENMASK(2, 0)
#define CS35L45_AUX_NGATE_CH_HOLD_DEFAULT 0x03
#define CS35L45_AUX_NGATE_CH_THR_DEFAULT 0x03
#define CS35L45_MAX_CACHE_REG 0x0000006B
#define CS35L45_MAX_PLL_CONFIGS 64
#define CS35L45_REGSTRIDE 4
#define CS35L45_VALID_PDATA 0x80000000
#define CS35L45_DEFAULT_SLOT_WIDTH 32
#define CS35L45_BUFSIZE 64
#define CS35L45_ALGID 0xCD
#define CS35L45_ALGID_MDSYNC 0xF20A
struct cs35l45_private;
struct cs35l45_pll_sysclk_config {
int freq;
int clk_cfg;
};
enum cspl_mboxstate {
CSPL_MBOX_STS_RUNNING = 0,
CSPL_MBOX_STS_PAUSED = 1,
CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
CSPL_MBOX_STS_HIBERNATE = 3,
CSPL_MBOX_STS_RECONFIGURING = 4,
};
enum cspl_mboxcmd {
CSPL_MBOX_CMD_NONE = 0,
CSPL_MBOX_CMD_PAUSE = 1,
CSPL_MBOX_CMD_RESUME = 2,
CSPL_MBOX_CMD_REINIT = 3,
CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
CSPL_MBOX_CMD_HIBERNATE = 5,
CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,
CSPL_MBOX_CMD_PREPARE_RECONFIGURATION = 7,
CSPL_MBOX_CMD_APPLY_RECONFIGURATION = 8,
CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
};
enum cspl_cmd {
CSPL_CMD_NONE = 0,
CSPL_CMD_MUTE = 1,
CSPL_CMD_UNMUTE = 2,
CSPL_CMD_UPDATE_PARAM = 8,
};
enum cspl_st {
CSPL_ST_RUNNING = 0,
CSPL_ST_ERROR = 1,
CSPL_ST_MUTED = 2,
CSPL_ST_REINITING = 3,
CSPL_ST_DIAGNOSING = 6,
};
enum pcm_mixers {
ASP_TX1 = 0,
ASP_TX2,
ASP_TX3,
ASP_TX4,
DSP_RX1,
DSP_RX2,
DSP_RX3,
DSP_RX4,
DSP_RX5,
DSP_RX6,
DSP_RX7,
DSP_RX8,
DACPCM,
NGATE1,
NGATE2,
};
enum amp_mode {
AMP_MODE_SPK = 0,
AMP_MODE_RCV = 1,
};
enum hiber_mode {
HIBER_MODE_DIS = 0,
HIBER_MODE_EN = 1,
};
enum dapm_route_mode {
DAPM_MODE_ASP = 0,
DAPM_MODE_DSP_SLAVE = 1,
DAPM_MODE_DSP_MASTER = 2,
};
bool cs35l45_readable_reg(struct device *dev, unsigned int reg);
bool cs35l45_volatile_reg(struct device *dev, unsigned int reg);
bool cs35l45_precious_reg(struct device *dev, unsigned int reg);
int cs35l45_set_csplmboxcmd(struct cs35l45_private *cs35l45,
enum cspl_mboxcmd cmd);
extern const struct reg_default cs35l45_reg[CS35L45_MAX_CACHE_REG];
extern const struct cs35l45_pll_sysclk_config
cs35l45_pll_sysclk[CS35L45_MAX_PLL_CONFIGS];
#endif /*__CS35L45_H__*/

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/*
* linux/sound/cs35l45.h -- Platform data for CS35L45
*
* Copyright 2019 Cirrus Logic, Inc.
*
* Author: James Schulman <james.schulman@cirrus.com>
*
*/
#ifndef __CS35L45_USER_H
#define __CS35L45_USER_H
#define CS35L45_NUM_SUPPLIES 2
struct bst_bpe_inst_lvl_config {
unsigned int thld;
unsigned int ilim;
unsigned int ss_ilim;
unsigned int atk_rate;
unsigned int hold_time;
unsigned int rls_rate;
};
struct bst_bpe_inst_config {
bool is_present;
struct bst_bpe_inst_lvl_config l0;
struct bst_bpe_inst_lvl_config l1;
struct bst_bpe_inst_lvl_config l2;
struct bst_bpe_inst_lvl_config l3;
struct bst_bpe_inst_lvl_config l4;
};
struct bst_bpe_misc_config {
bool is_present;
unsigned int bst_bpe_inst_inf_hold_rls;
unsigned int bst_bpe_il_lim_mode;
unsigned int bst_bpe_out_opmode_sel;
unsigned int bst_bpe_inst_l3_byp;
unsigned int bst_bpe_inst_l2_byp;
unsigned int bst_bpe_inst_l1_byp;
unsigned int bst_bpe_filt_sel;
};
struct bst_bpe_il_lim_config {
bool is_present;
unsigned int bst_bpe_il_lim_thld_del1;
unsigned int bst_bpe_il_lim_thld_del2;
unsigned int bst_bpe_il_lim1_thld;
unsigned int bst_bpe_il_lim1_dly;
unsigned int bst_bpe_il_lim2_dly;
unsigned int bst_bpe_il_lim_dly_hyst;
unsigned int bst_bpe_il_lim_thld_hyst;
unsigned int bst_bpe_il_lim1_atk_rate;
unsigned int bst_bpe_il_lim2_atk_rate;
unsigned int bst_bpe_il_lim1_rls_rate;
unsigned int bst_bpe_il_lim2_rls_rate;
};
struct hvlv_config {
bool is_present;
unsigned int hvlv_thld_hys;
unsigned int hvlv_thld;
unsigned int hvlv_dly;
};
struct ldpm_config {
bool is_present;
unsigned int ldpm_gp1_boost_sel;
unsigned int ldpm_gp1_amp_sel;
unsigned int ldpm_gp1_delay;
unsigned int ldpm_gp1_pcm_thld;
unsigned int ldpm_gp2_imon_sel;
unsigned int ldpm_gp2_vmon_sel;
unsigned int ldpm_gp2_delay;
unsigned int ldpm_gp2_pcm_thld;
};
struct classh_config {
bool is_present;
unsigned int ch_hdrm;
unsigned int ch_ratio;
unsigned int ch_rel_rate;
unsigned int ch_ovb_thld1;
unsigned int ch_ovb_thlddelta;
unsigned int ch_vdd_bst_max;
unsigned int ch_ovb_ratio;
unsigned int ch_thld1_offset;
unsigned int aud_mem_depth;
};
struct gpio_ctrl {
bool is_present;
unsigned int dir;
unsigned int lvl;
unsigned int op_cfg;
unsigned int pol;
unsigned int ctrl;
unsigned int invert;
};
struct cs35l45_irq_monitor {
unsigned int reg;
unsigned int mask;
unsigned int bitmask;
const char *description;
const char *err_msg;
int (*callback)(struct cs35l45_private *cs35l45);
};
struct cs35l45_platform_data {
struct bst_bpe_inst_config bst_bpe_inst_cfg;
struct bst_bpe_misc_config bst_bpe_misc_cfg;
struct bst_bpe_il_lim_config bst_bpe_il_lim_cfg;
struct hvlv_config hvlv_cfg;
struct ldpm_config ldpm_cfg;
struct classh_config classh_cfg;
struct gpio_ctrl gpio_ctrl1;
struct gpio_ctrl gpio_ctrl2;
struct gpio_ctrl gpio_ctrl3;
const char *dsp_part_name;
unsigned int asp_sdout_hiz_ctrl;
unsigned int ngate_ch1_hold;
unsigned int ngate_ch1_thr;
unsigned int ngate_ch2_hold;
unsigned int ngate_ch2_thr;
bool use_tdm_slots;
};
struct cs35l45_private {
struct wm_adsp dsp; /* needs to be first member */
struct device *dev;
struct regmap *regmap;
struct gpio_desc *reset_gpio;
struct regulator_bulk_data supplies[CS35L45_NUM_SUPPLIES];
struct cs35l45_platform_data pdata;
struct work_struct dsp_pmd_work;
struct mutex rate_lock;
struct mutex dsp_pmd_lock;
enum dapm_route_mode dapm_mode;
bool initialized;
bool fast_switch_en;
unsigned int wksrc;
unsigned int i2c_addr;
unsigned int sync_num_devices;
unsigned int sync_id;
int irq;
int slot_width;
int amplifier_mode;
int hibernate_mode;
/* Run-time mixer */
struct snd_kcontrol_new fast_ctl;
unsigned int fast_switch_file_idx;
struct soc_enum fast_switch_enum;
const char **fast_switch_names;
/* Downstream specific */
unsigned int dig_vol;
int dsp1_enable_pin;
unsigned int global_err_rls;
};
int cs35l45_initialize(struct cs35l45_private *cs35l45);
int cs35l45_probe(struct cs35l45_private *cs35l45);
int cs35l45_remove(struct cs35l45_private *cs35l45);
struct of_entry {
const char *name;
unsigned int reg;
unsigned int mask;
unsigned int shift;
};
enum bst_bpe_inst_level {
L0 = 0,
L1,
L2,
L3,
L4,
BST_BPE_INST_LEVELS
};
enum bst_bpe_inst_of_param {
BST_BPE_INST_THLD = 0,
BST_BPE_INST_ILIM,
BST_BPE_INST_SS_ILIM,
BST_BPE_INST_ATK_RATE,
BST_BPE_INST_HOLD_TIME,
BST_BPE_INST_RLS_RATE,
BST_BPE_INST_PARAMS
};
enum bst_bpe_misc_of_param {
BST_BPE_INST_INF_HOLD_RLS = 0,
BST_BPE_IL_LIM_MODE,
BST_BPE_OUT_OPMODE_SEL,
BST_BPE_INST_L3_BYP,
BST_BPE_INST_L2_BYP,
BST_BPE_INST_L1_BYP,
BST_BPE_FILT_SEL,
BST_BPE_MISC_PARAMS
};
enum bst_bpe_il_lim_of_param {
BST_BPE_IL_LIM_THLD_DEL1 = 0,
BST_BPE_IL_LIM_THLD_DEL2,
BST_BPE_IL_LIM1_THLD,
BST_BPE_IL_LIM1_DLY,
BST_BPE_IL_LIM2_DLY,
BST_BPE_IL_LIM_DLY_HYST,
BST_BPE_IL_LIM_THLD_HYST,
BST_BPE_IL_LIM1_ATK_RATE,
BST_BPE_IL_LIM2_ATK_RATE,
BST_BPE_IL_LIM1_RLS_RATE,
BST_BPE_IL_LIM2_RLS_RATE,
BST_BPE_IL_LIM_PARAMS
};
enum ldpm_of_param {
LDPM_GP1_BOOST_SEL = 0,
LDPM_GP1_AMP_SEL,
LDPM_GP1_DELAY,
LDPM_GP1_PCM_THLD,
LDPM_GP2_IMON_SEL,
LDPM_GP2_VMON_SEL,
LDPM_GP2_DELAY,
LDPM_GP2_PCM_THLD,
LDPM_PARAMS
};
enum classh_of_param {
CH_HDRM = 0,
CH_RATIO,
CH_REL_RATE,
CH_OVB_THLD1,
CH_OVB_THLDDELTA,
CH_VDD_BST_MAX,
CH_OVB_RATIO,
CH_THLD1_OFFSET,
AUD_MEM_DEPTH,
CLASSH_PARAMS
};
extern const struct of_entry bst_bpe_inst_thld_map[BST_BPE_INST_LEVELS];
extern const struct of_entry bst_bpe_inst_ilim_map[BST_BPE_INST_LEVELS];
extern const struct of_entry bst_bpe_inst_ss_ilim_map[BST_BPE_INST_LEVELS];
extern const struct of_entry bst_bpe_inst_atk_rate_map[BST_BPE_INST_LEVELS];
extern const struct of_entry bst_bpe_inst_hold_time_map[BST_BPE_INST_LEVELS];
extern const struct of_entry bst_bpe_inst_rls_rate_map[BST_BPE_INST_LEVELS];
extern const struct of_entry bst_bpe_misc_map[BST_BPE_MISC_PARAMS];
extern const struct of_entry bst_bpe_il_lim_map[BST_BPE_IL_LIM_PARAMS];
extern const struct of_entry ldpm_map[LDPM_PARAMS];
extern const struct of_entry classh_map[CLASSH_PARAMS];
static inline const struct of_entry *cs35l45_get_bst_bpe_inst_entry(
enum bst_bpe_inst_level level,
enum bst_bpe_inst_of_param param)
{
if ((level < L0) || (level > L4))
return NULL;
switch (param) {
case BST_BPE_INST_THLD:
return &bst_bpe_inst_thld_map[level];
case BST_BPE_INST_ILIM:
return &bst_bpe_inst_ilim_map[level];
case BST_BPE_INST_SS_ILIM:
return &bst_bpe_inst_ss_ilim_map[level];
case BST_BPE_INST_ATK_RATE:
return &bst_bpe_inst_atk_rate_map[level];
case BST_BPE_INST_HOLD_TIME:
return &bst_bpe_inst_hold_time_map[level];
case BST_BPE_INST_RLS_RATE:
return &bst_bpe_inst_rls_rate_map[level];
default:
return NULL;
}
}
static inline u32 *cs35l45_get_bst_bpe_inst_param(
struct cs35l45_private *cs35l45,
enum bst_bpe_inst_level level,
enum bst_bpe_inst_of_param param)
{
struct bst_bpe_inst_lvl_config *cfg;
switch (level) {
case L0:
cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l0;
break;
case L1:
cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l1;
break;
case L2:
cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l2;
break;
case L3:
cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l3;
break;
case L4:
cfg = &cs35l45->pdata.bst_bpe_inst_cfg.l4;
break;
default:
return NULL;
}
switch (param) {
case BST_BPE_INST_THLD:
return &cfg->thld;
case BST_BPE_INST_ILIM:
return &cfg->ilim;
case BST_BPE_INST_SS_ILIM:
return &cfg->ss_ilim;
case BST_BPE_INST_ATK_RATE:
return &cfg->atk_rate;
case BST_BPE_INST_HOLD_TIME:
return &cfg->hold_time;
case BST_BPE_INST_RLS_RATE:
return &cfg->rls_rate;
default:
return NULL;
}
}
static inline u32 *cs35l45_get_bst_bpe_misc_param(
struct cs35l45_private *cs35l45,
enum bst_bpe_misc_of_param param)
{
struct bst_bpe_misc_config *cfg = &cs35l45->pdata.bst_bpe_misc_cfg;
switch (param) {
case BST_BPE_INST_INF_HOLD_RLS:
return &cfg->bst_bpe_inst_inf_hold_rls;
case BST_BPE_IL_LIM_MODE:
return &cfg->bst_bpe_il_lim_mode;
case BST_BPE_OUT_OPMODE_SEL:
return &cfg->bst_bpe_out_opmode_sel;
case BST_BPE_INST_L3_BYP:
return &cfg->bst_bpe_inst_l3_byp;
case BST_BPE_INST_L2_BYP:
return &cfg->bst_bpe_inst_l2_byp;
case BST_BPE_INST_L1_BYP:
return &cfg->bst_bpe_inst_l1_byp;
case BST_BPE_FILT_SEL:
return &cfg->bst_bpe_filt_sel;
default:
return NULL;
}
}
static inline u32 *cs35l45_get_bst_bpe_il_lim_param(
struct cs35l45_private *cs35l45,
enum bst_bpe_il_lim_of_param param)
{
struct bst_bpe_il_lim_config *cfg = &cs35l45->pdata.bst_bpe_il_lim_cfg;
switch (param) {
case BST_BPE_IL_LIM_THLD_DEL1:
return &cfg->bst_bpe_il_lim_thld_del1;
case BST_BPE_IL_LIM_THLD_DEL2:
return &cfg->bst_bpe_il_lim_thld_del2;
case BST_BPE_IL_LIM1_THLD:
return &cfg->bst_bpe_il_lim1_thld;
case BST_BPE_IL_LIM1_DLY:
return &cfg->bst_bpe_il_lim1_dly;
case BST_BPE_IL_LIM2_DLY:
return &cfg->bst_bpe_il_lim2_dly;
case BST_BPE_IL_LIM_DLY_HYST:
return &cfg->bst_bpe_il_lim_dly_hyst;
case BST_BPE_IL_LIM_THLD_HYST:
return &cfg->bst_bpe_il_lim_thld_hyst;
case BST_BPE_IL_LIM1_ATK_RATE:
return &cfg->bst_bpe_il_lim1_atk_rate;
case BST_BPE_IL_LIM2_ATK_RATE:
return &cfg->bst_bpe_il_lim2_atk_rate;
case BST_BPE_IL_LIM1_RLS_RATE:
return &cfg->bst_bpe_il_lim1_rls_rate;
case BST_BPE_IL_LIM2_RLS_RATE:
return &cfg->bst_bpe_il_lim2_rls_rate;
default:
return NULL;
}
}
static inline u32 *cs35l45_get_ldpm_param(struct cs35l45_private *cs35l45,
enum ldpm_of_param param)
{
struct ldpm_config *cfg = &cs35l45->pdata.ldpm_cfg;
switch (param) {
case LDPM_GP1_BOOST_SEL:
return &cfg->ldpm_gp1_boost_sel;
case LDPM_GP1_AMP_SEL:
return &cfg->ldpm_gp1_amp_sel;
case LDPM_GP1_DELAY:
return &cfg->ldpm_gp1_delay;
case LDPM_GP1_PCM_THLD:
return &cfg->ldpm_gp1_pcm_thld;
case LDPM_GP2_IMON_SEL:
return &cfg->ldpm_gp2_imon_sel;
case LDPM_GP2_VMON_SEL:
return &cfg->ldpm_gp2_vmon_sel;
case LDPM_GP2_DELAY:
return &cfg->ldpm_gp2_delay;
case LDPM_GP2_PCM_THLD:
return &cfg->ldpm_gp2_pcm_thld;
default:
return NULL;
}
}
static inline u32 *cs35l45_get_classh_param(struct cs35l45_private *cs35l45,
enum classh_of_param param)
{
struct classh_config *cfg = &cs35l45->pdata.classh_cfg;
switch (param) {
case CH_HDRM:
return &cfg->ch_hdrm;
case CH_RATIO:
return &cfg->ch_ratio;
case CH_REL_RATE:
return &cfg->ch_rel_rate;
case CH_OVB_THLD1:
return &cfg->ch_ovb_thld1;
case CH_OVB_THLDDELTA:
return &cfg->ch_ovb_thlddelta;
case CH_VDD_BST_MAX:
return &cfg->ch_vdd_bst_max;
case CH_OVB_RATIO:
return &cfg->ch_ovb_ratio;
case CH_THLD1_OFFSET:
return &cfg->ch_thld1_offset;
case AUD_MEM_DEPTH:
return &cfg->aud_mem_depth;
default:
return NULL;
}
}
#endif /* __CS35L45_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* wm_adsp.h -- Wolfson ADSP support
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*/
#ifndef __WM_ADSP_H
#define __WM_ADSP_H
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/compress_driver.h>
#include "wmfw.h"
/* Return values for wm_adsp_compr_handle_irq */
#define WM_ADSP_COMPR_OK 0
#define WM_ADSP_COMPR_VOICE_TRIGGER 1
#define WM_ADSP2_REGION_0 BIT(0)
#define WM_ADSP2_REGION_1 BIT(1)
#define WM_ADSP2_REGION_2 BIT(2)
#define WM_ADSP2_REGION_3 BIT(3)
#define WM_ADSP2_REGION_4 BIT(4)
#define WM_ADSP2_REGION_5 BIT(5)
#define WM_ADSP2_REGION_6 BIT(6)
#define WM_ADSP2_REGION_7 BIT(7)
#define WM_ADSP2_REGION_8 BIT(8)
#define WM_ADSP2_REGION_9 BIT(9)
#define WM_ADSP2_REGION_1_9 (WM_ADSP2_REGION_1 | \
WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \
WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | \
WM_ADSP2_REGION_6 | WM_ADSP2_REGION_7 | \
WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9)
#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9)
struct wm_adsp_region {
int type;
unsigned int base;
};
struct wm_adsp_alg_region {
struct list_head list;
unsigned int alg;
int type;
unsigned int base;
};
struct wm_adsp_compr;
struct wm_adsp_compr_buf;
struct wm_adsp_ops;
struct wm_adsp {
const char *part;
const char *name;
const char *fwf_name;
int rev;
int num;
int type;
struct device *dev;
struct regmap *regmap;
struct snd_soc_component *component;
struct wm_adsp_ops *ops;
unsigned int base;
unsigned int base_sysinfo;
unsigned int sysclk_reg;
unsigned int sysclk_mask;
unsigned int sysclk_shift;
// Speaker calibration parameters
int cal_z;
int ambient;
int cal_status;
int cal_chksum;
struct list_head alg_regions;
unsigned int fw_id;
unsigned int fw_id_version;
unsigned int fw_vendor_id;
const struct wm_adsp_region *mem;
int num_mems;
int fw;
int fw_ver;
bool no_preloader;
bool preloaded;
bool booted;
bool running;
bool fatal_error;
struct list_head ctl_list;
struct work_struct boot_work;
struct list_head compr_list;
struct list_head buffer_list;
struct mutex pwr_lock;
unsigned int lock_regions;
unsigned int n_rx_channels;
unsigned int n_tx_channels;
struct mutex *rate_lock;
u8 *rx_rate_cache;
u8 *tx_rate_cache;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_root;
char *wmfw_file_name;
char *bin_file_name;
#endif
unsigned int data_word_mask;
int data_word_size;
void (*fwevent_cb)(struct wm_adsp *dsp, int eventid);
};
struct wm_adsp_ops {
unsigned int sys_config_size;
bool (*validate_version)(struct wm_adsp *dsp, unsigned int version);
unsigned int (*parse_sizes)(struct wm_adsp *dsp,
const char * const file,
unsigned int pos,
const struct firmware *firmware);
int (*setup_algs)(struct wm_adsp *dsp);
unsigned int (*region_to_reg)(struct wm_adsp_region const *mem,
unsigned int offset);
void (*show_fw_status)(struct wm_adsp *dsp);
void (*stop_watchdog)(struct wm_adsp *dsp);
int (*enable_memory)(struct wm_adsp *dsp);
void (*disable_memory)(struct wm_adsp *dsp);
int (*lock_memory)(struct wm_adsp *dsp, unsigned int lock_regions);
int (*enable_core)(struct wm_adsp *dsp);
void (*disable_core)(struct wm_adsp *dsp);
int (*start_core)(struct wm_adsp *dsp);
void (*stop_core)(struct wm_adsp *dsp);
};
#define WM_ADSP_PRELOADER(wname, num, event_fn) \
{ .id = snd_soc_dapm_supply, .name = wname " Preloader", \
.reg = SND_SOC_NOPM, .shift = num, .event = event_fn, \
.event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \
.subseq = 100, /* Ensure we run after SYSCLK supply widget */ }
#define WM_ADSP1(wname, num) \
SND_SOC_DAPM_PGA_E(wname, SND_SOC_NOPM, num, 0, NULL, 0, \
wm_adsp1_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD)
#define WM_ADSP2_PRELOAD_SWITCH(wname, num) \
SOC_SINGLE_EXT(wname " Preload Switch", SND_SOC_NOPM, num, 1, 0, \
wm_adsp2_preloader_get, wm_adsp2_preloader_put)
#define WM_ADSP2(wname, num, event_fn) \
SND_SOC_DAPM_SPK(wname " Preload", NULL), \
WM_ADSP_PRELOADER(wname, num, event_fn), \
{ .id = snd_soc_dapm_out_drv, .name = wname, \
.reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp_event, \
.event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD }
#define WM_HALO(wname, num, event_fn) \
WM_ADSP2(wname, num, event_fn)
#define WM_ADSP_FW_CONTROL(dspname, num) \
SOC_ENUM_EXT(dspname " Firmware", wm_adsp_fw_enum[num], \
wm_adsp_fw_get, wm_adsp_fw_put)
extern const struct soc_enum wm_adsp_fw_enum[];
int wm_adsp1_init(struct wm_adsp *dsp);
int wm_adsp2_init(struct wm_adsp *dsp);
void wm_adsp2_remove(struct wm_adsp *dsp);
int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component);
int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component);
int wm_vpu_init(struct wm_adsp *vpu);
int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock);
int wm_adsp1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
int wm_adsp_early_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
irqreturn_t wm_adsp2_bus_error(int irq, void *data);
irqreturn_t wm_halo_bus_error(int irq, void *data);
irqreturn_t wm_halo_wdt_expire(int irq, void *data);
int wm_adsp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event);
int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq);
int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream);
int wm_adsp_compr_free(struct snd_compr_stream *stream);
int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
struct snd_compr_params *params);
int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
struct snd_compr_caps *caps);
int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd);
int wm_adsp_compr_handle_irq(struct wm_adsp *dsp);
int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
struct snd_compr_tstamp *tstamp);
int wm_adsp_compr_copy(struct snd_compr_stream *stream,
char __user *buf, size_t count);
int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type,
unsigned int alg, void *buf, size_t len);
int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type,
unsigned int alg, void *buf, size_t len);
extern int wm_adsp_handle_fw_event(struct wm_adsp *dsp);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* wmfw.h - Wolfson firmware format information
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*/
#ifndef __WMFW_H
#define __WMFW_H
#include <linux/types.h>
#define WMFW_MAX_ALG_NAME 256
#define WMFW_MAX_ALG_DESCR_NAME 256
#define WMFW_MAX_COEFF_NAME 256
#define WMFW_MAX_COEFF_DESCR_NAME 256
#define WMFW_CTL_FLAG_SYS 0x8000
#define WMFW_CTL_FLAG_VOLATILE 0x0004
#define WMFW_CTL_FLAG_WRITEABLE 0x0002
#define WMFW_CTL_FLAG_READABLE 0x0001
/* Non-ALSA coefficient types start at 0x1000 */
#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */
#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */
#define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */
#define WMFW_CTL_TYPE_FWEVENT 0x1004 /* firmware event control */
struct wmfw_header {
char magic[4];
__le32 len;
__le16 rev;
u8 core;
u8 ver;
} __packed;
struct wmfw_footer {
__le64 timestamp;
__le32 checksum;
} __packed;
struct wmfw_adsp1_sizes {
__le32 dm;
__le32 pm;
__le32 zm;
} __packed;
struct wmfw_adsp2_sizes {
__le32 xm;
__le32 ym;
__le32 pm;
__le32 zm;
} __packed;
struct wmfw_vpu_sizes {
__le32 dm;
} __packed;
struct wmfw_region {
union {
__be32 type;
__le32 offset;
};
__le32 len;
u8 data[];
} __packed;
struct wmfw_id_hdr {
__be32 core_id;
__be32 core_rev;
__be32 id;
__be32 ver;
} __packed;
struct wmfw_v3_id_hdr {
__be32 core_id;
__be32 block_rev;
__be32 vendor_id;
__be32 id;
__be32 ver;
} __packed;
struct wmfw_adsp1_id_hdr {
struct wmfw_id_hdr fw;
__be32 zm;
__be32 dm;
__be32 n_algs;
} __packed;
struct wmfw_adsp2_id_hdr {
struct wmfw_id_hdr fw;
__be32 zm;
__be32 xm;
__be32 ym;
__be32 n_algs;
} __packed;
struct wmfw_halo_id_hdr {
struct wmfw_v3_id_hdr fw;
__be32 xm_base;
__be32 xm_size;
__be32 ym_base;
__be32 ym_size;
__be32 n_algs;
} __packed;
struct wmfw_vpu_id_hdr {
struct wmfw_v3_id_hdr fw;
__be32 dm_base;
__be32 dm_size;
__be32 n_algs;
} __packed;
struct wmfw_alg_hdr {
__be32 id;
__be32 ver;
} __packed;
struct wmfw_adsp1_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 zm;
__be32 dm;
} __packed;
struct wmfw_adsp2_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 zm;
__be32 xm;
__be32 ym;
} __packed;
struct wmfw_vpu_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 dm_base;
__be32 dm_size;
} __packed;
struct wmfw_halo_alg_hdr {
struct wmfw_alg_hdr alg;
__be32 xm_base;
__be32 xm_size;
__be32 ym_base;
__be32 ym_size;
} __packed;
struct wmfw_adsp_alg_data {
__le32 id;
u8 name[WMFW_MAX_ALG_NAME];
u8 descr[WMFW_MAX_ALG_DESCR_NAME];
__le32 ncoeff;
u8 data[];
} __packed;
struct wmfw_adsp_coeff_data {
struct {
__le16 offset;
__le16 type;
__le32 size;
} hdr;
u8 name[WMFW_MAX_COEFF_NAME];
u8 descr[WMFW_MAX_COEFF_DESCR_NAME];
__le16 ctl_type;
__le16 flags;
__le32 len;
u8 data[];
} __packed;
struct wmfw_coeff_hdr {
u8 magic[4];
__le32 len;
union {
__be32 rev;
__le32 ver;
};
union {
__be32 core;
__le32 core_ver;
};
u8 data[];
} __packed;
struct wmfw_coeff_item {
__le16 offset;
__le16 type;
__le32 id;
__le32 ver;
__le32 sr;
__le32 len;
u8 data[];
} __packed;
#define WMFW_ADSP1 1
#define WMFW_ADSP2 2
#define WMFW_HALO 4
#define WMFW_VPU 0x45
#define WMFW_ABSOLUTE 0xf0
#define WMFW_ALGORITHM_DATA 0xf2
#define WMFW_METADATA 0xfc
#define WMFW_NAME_TEXT 0xfe
#define WMFW_INFO_TEXT 0xff
#define WMFW_ADSP1_PM 2
#define WMFW_ADSP1_DM 3
#define WMFW_ADSP1_ZM 4
#define WMFW_ADSP2_PM 2
#define WMFW_ADSP2_ZM 4
#define WMFW_ADSP2_XM 5
#define WMFW_ADSP2_YM 6
#define WMFW_HALO_PM_PACKED 0x10
#define WMFW_HALO_XM_PACKED 0x11
#define WMFW_HALO_YM_PACKED 0x12
#define WMFW_VPU_DM 0x30
#endif