lisa/android_kernel_xiaomi_sm8350
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

soc: swr: update interval high register

Browse Source 
Update interval high register.

Change-Id: I7c56ba801545f14607796977a976e535cf9da6ca
Signed-off-by: Meng Wang <mengw@codeaurora.org>
This commit is contained in:
Meng Wang 2020-04-01 14:44:47 +08:00 committed by Gerrit - the friendly Code Review server
parent 848466a9cc
commit 96262c74ed
2 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
soc/swr-mstr-ctrl.c
View File

@ -1275,10 +1275,16 @@ static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
bank));
reg[len] = SWRM_CMD_FIFO_WR_CMD;
val[len++] = SWR_REG_VAL_PACK(mport->sinterval,
val[len++] = SWR_REG_VAL_PACK(mport->sinterval & 0xFF,
port_req->dev_num, 0x00,
SWRS_DP_SAMPLE_CONTROL_1_BANK(slv_id,
bank));
reg[len] = SWRM_CMD_FIFO_WR_CMD;
val[len++] = SWR_REG_VAL_PACK((mport->sinterval >> 8)& 0xFF,
port_req->dev_num, 0x00,
SWRS_DP_SAMPLE_CONTROL_2_BANK(slv_id,
bank));
/* Assumption: If different channels in the same port
* on master is enabled for different slaves, then each
* slave offset should be configured differently.

2
soc/swrm_registers.h
View File

@ -232,6 +232,8 @@
SWRS_DP_REG_OFFSET(n, m))
#define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x122 + \
SWRS_DP_REG_OFFSET(n, m))
#define SWRS_DP_SAMPLE_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x123 + \
SWRS_DP_REG_OFFSET(n, m))
#define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x124 + \
SWRS_DP_REG_OFFSET(n, m))
#define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x125 + \