Commit Graph

2025 Commits

Author SHA1 Message Date
osaisruj
1e20848d49 disp: msm: add support for twm entry
Skip backlight updates and panel off commands
during twm entry.

Change-Id: I7656fa0d513a8a3e82d9bbbf5c3f85c1b84ee9da
Signed-off-by: osaisruj <osaisruj@codeaurora.org>
2021-11-10 12:38:14 +05:30
osaisruj
05ccf7d278 disp: msm: sde: add twm mode sysfs mode
Add sysfs node on connector to get twm enable
state. This node is used by the HAL to notify TWM
entry and exit.

Change-Id: I56a844076014c2e12075756f6b1bc42b91b48ad1
Signed-off-by: osaisruj <osaisruj@codeaurora.org>
2021-11-10 12:24:04 +05:30
osaisruj
0dd45aa272 disp: msm: sde: add sysfs node to give panel power state
Add sysfs node on connecter to get the panel power state.
This node is used by the HAL to read display power state.

Change-Id: I717e4b87513a845c867871f93876fc7c88ff7b2f
Signed-off-by: osaisruj <osaisruj@codeaurora.org>
2021-11-10 12:15:27 +05:30
Jayaprakash Madisetty
b71e9dc15f disp: msm: sde: avoid rsvp_nxt allocation for suspend commit
During suspend commit, crtc_commit thread is blocked waiting
for touch response in drm_panel_notifier_call_chain and
rsvp_nxt pointer clear in drm_atomic_state_put is pending
(>100ms wait) which was allocated in atomic_check. When
resume commit is triggered early, RM poll timeouts are seen
due to rsvp_nxt pointer is not cleared and thus causing
power on commit failures. This change avoids RM reserve
during atomic_check of suspend commit as msm_crtc_set_mode
returns early and rsvp_nxt is not used elsewhere in commit path.

Change-Id: I4e7bb41d38f5b88ee75f63007dc4403b6b903265
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
2021-11-03 16:10:51 +05:30
Jayaprakash Madisetty
a245be26e4 disp: msm: sde: add changes to allocate compatible cwb mixers in RM
This change parses new dt property CWB_MIXER_MASK, which signifies
the compatible mixer_mask for the corresponding CWB block.
During mixer allocation for CWB usecase, we use this cwb_mixer_mask
to decide compatible mixers for built-in primary and secondary displays.

In the current issue case, mixer allocation is as below in
multi display usecase:

primary: LM0
secondary: LM1
external: LM2

RM loops through available mixers and tries to allocate LM3 when
CWB is triggered on primary display. But from HW perspective,
LM0 is not muxed to LM3 causing wb timeouts. With current change
LM3 gets skipped and LM4 gets allocated.

Change-Id: I95ce16a083c9b9976a9dff309d7754085ee08958
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
2021-10-22 11:00:26 +05:30
qctecmdr
8a46f8f341 Merge "disp: msm: sde: add evt log in rsc timer calculation" 2021-10-21 08:11:20 -07:00
qctecmdr
595270c421 Merge "msm: disp: rotator: add ROT macros for logs" 2021-10-21 08:11:20 -07:00
qctecmdr
a9e9c3d500 Merge "disp: msm: dp: replace pr_err with DP_ERR" 2021-10-21 08:11:20 -07:00
qctecmdr
a7844b99e6 Merge "disp: msm: sde: disable CWB crop after cwb session is ended" 2021-10-21 08:11:20 -07:00
Andhavarapu Karthik
cf6ecb4214 disp: msm: sde: add evt log in rsc timer calculation
This change adds required log in rsc timer calculation.

Change-Id: If16487ae8783651b3a2ac4839928a15131b678ee
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
2021-10-20 13:12:06 +05:30
Kalyan Thota
c03772f2f2 msm: disp: rotator: add ROT macros for logs
Avoid pr_err and use SDEROT macros for console
logging.

Change-Id: I4c0c6cf1d482a55f82c73572b1327695b85c5501
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
2021-10-19 23:39:02 -07:00
Soutrik Mukhopadhyay
1cbd7ae152 disp: msm: dp: replace pr_err with DP_ERR
This change replaces pr_err with DP_ERR in dp_display
driver source code.

Change-Id: I5c621ead001c5b9364511495fceba1aa7f41488d
Signed-off-by: Soutrik Mukhopadhyay <mukhopad@codeaurora.org>
2021-10-19 20:20:01 +05:30
Rajeev Nandan
c0783f528e disp: msm: dsi: Do not call devm_clk_put() with invalid clk
Do not call devm_clk_put() if devm_clk_get() was failed for
a given clk. The devm_clk_put() does not check for the validity
of the input clk argumnet, and can cause NULL pointer dereference
or some other errors if called with invalid clk argument.

Change-Id: Ie626a5afed52a146ebd1a2092c7d9db9226dbfe0
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2021-10-19 06:49:54 -07:00
qctecmdr
4b054fac24 Merge "disp: rotator: remove warning log from spin_lock" 2021-10-19 03:05:11 -07:00
Krishna Manikandan
c667c77f1f disp: msm: sde: disable CWB crop after cwb session is ended
Add changes to disable CWB crop params as part of writeback
disable.

Change-Id: I18582ceb502e759ec4b67568562ac95ff3f0d359
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2021-10-19 10:33:01 +05:30
Mahadevan
018e528ec3 disp: rotator: remove warning log from spin_lock
On rotator commit failure resync timeline will
happen which gives continuous warning logs in
console leads to cpu throttling. To resolve this
the warning message is removed from spin_lock.

Change-Id: I5ce66413556518668769cad3bc6a900f9bdada4b
Signed-off-by: Mahadevan <mahap@codeaurora.org>
2021-10-18 17:56:50 +05:30
Krishna Manikandan
070934308c disp: msm: sde: protect file private structure with mutex lock
Access file private data structures inside the
mutex lock only to avoid use-after-free issues.

Change-Id: If70731f517bcb47d4515f131fecafe702064cb45
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2021-10-08 10:36:19 +05:30
osaisruj
5599d64b44 disp: msm: dsi: add support for ultra low power state
During lp2 state the load on the panel and
controller regulators can be reduced. Configure ldos
in optimum mode during this state.

Change-Id: I75c180f28f636ebb23ecbe9679ba89c00977fe0f
Signed-off-by: osaisruj <osaisruj@codeaurora.org>
2021-10-01 11:20:21 +05:30
qctecmdr
5d29dc4215 Merge "disp: msm: sde: add checks to avoid null pointer dereference" 2021-09-24 05:41:33 -07:00
qctecmdr
46726a0d62 Merge "disp: msm: sde: switch rsc state before CTL_PREPARE in dual display" 2021-09-24 05:41:33 -07:00
Mahadevan
ae98505aae disp: msm: sde: switch rsc state before CTL_PREPARE in dual display
In dual display usecase when both displays comes out of
idle following scenario will cause wr_ptr timeout.

 1. Both displays goes to idle and RSCC enters Mode-2.
 2. Primary display exit idle upon DRM commit N RSC
    enters Solver State.
 3. Secondary display exits idle upon DRM commit M and
    waits on input fence after CTL_1_PREPARE is set.
    RSC is still in CMD state.
 4. Primary Commit N frame transfer got successful and
    commit N+1 is queued in primary display when RSC
    in solver state which leads to timeout in primary.

This is because RSCC will not generate a wakeup in sync with
primary timelines leading to timeout. This is because RSCC
still sees idle low thinking frame transfer is taking long
time. This change will switch the rsc state to AMC mode
before CTL_PREPARE is set which resolves such issue.

Change-Id: Ic32e48b4febbbcc54d94876194d38fe6ef3d0981
Signed-off-by: Mahadevan <mahap@codeaurora.org>
2021-09-22 10:03:27 +05:30
Andhavarapu Karthik
92359a8a2e disp: msm: sde: add checks to avoid null pointer dereference
This change adds required checks to avoid accessing null pointer
where debug bus is not initialised and dumping the debug bus points.

Change-Id: Ia46a4b95706f05e37be660f006c04b1e2e9f6848
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-09-21 14:53:39 +05:30
Ritesh Kumar
d57c2eee47 drm: msm: dsi: Update DSI parser util to skip disabled child nodes
Currently, disabled timing child nodes or power supply nodes are
not skipped because of which status = "disabled" entry does not
work for child nodes. Use of_get_next_available_child to skip
disabled child nodes.

Change-Id: Ib6e4b655f83dd0ee3ffddd496976c34030fa3dc0
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-09-21 02:26:57 +05:30
qctecmdr
f6c68cc1dc Merge "disp: msm: dsi: Fix deadlock issue in debugfs_esd_trigger_check function" 2021-09-17 01:16:52 -07:00
qctecmdr
3e3f681b8a Merge "disp: msm: qpic: fix kw issues in QPIC display driver" 2021-09-17 01:16:52 -07:00
Lei Chen
ad3b81ed30 disp: msm: qpic: fix kw issues in QPIC display driver
This change is updated to address use after free and null checks
in QPIC display driver.

Change-Id: I97f1d941de69aad3d49cbf0c9782022b8f7db840
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-09-13 09:14:57 +08:00
qctecmdr
45aa3e5a37 Merge "disp: msm: sde: clear partial update mask during last close" 2021-09-09 09:42:38 -07:00
qctecmdr
f2a33e5cfe Merge "msm: sde: disp: Set merge_mode after vlut and hist enable" 2021-09-09 09:42:38 -07:00
Srihitha Tangudu
f6d96209a5 disp: msm: dsi: Fix deadlock issue in debugfs_esd_trigger_check function
In debugfs_esd_trigger_check, display mutex is not unlocked in error 
scenario which may lead to deadlock. This change adds fix to handle this.

Change-Id: I44d78959630a49bd1e9dcf871cfc108ac43232db
Signed-off-by: Srihitha Tangudu <tangudu@codeaurora.org>
2021-09-08 15:21:00 +05:30
Anjaneya Prasad Musunuri
1e1c1a4a1c disp: msm: sde: clear partial update mask during last close
Clear partial update mask during last close to avoid
rounded corner to be programmed without valid mask during
shell stop/start operations.

Change-Id: I378adc62b5bc5913abfc32fa3528c8e28ea273d4
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
2021-09-08 01:24:30 -07:00
Ping Li
a83f22243d msm: sde: disp: Set merge_mode after vlut and hist enable
To ensure that set merge_mode after vlut and hist enable, move merge_mode
enable from ltm_init to ltm_vlut.
Redefine the OP_MASK of LTM_INIT_ENABLE and LTM_VLUT_ENABLE, in order to
write the merge_mode bits correctly.

Change-Id: I5258e7f545e265b114098e46d31986274127e962
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
2021-09-08 14:19:46 +08:00
qctecmdr
6c7d4ccc36 Merge "disp: msm: sde: use fixed prefill lines in rscc static wakeup calculation" 2021-09-03 02:17:28 -07:00
qctecmdr
862239a2f3 Merge "disp: msm: fix dsi debugbus in-mem logging" 2021-08-31 21:32:04 -07:00
Jayaprakash Madisetty
b45b583f53 disp: msm: sde: use fixed prefill lines in rscc static wakeup calculation
In dual display during bootup, panel prefill lines may be used in
configuring rscc static wakeup due to ongoing autorefresh in secondary
display. Due to this, there can be a case when transfer time for the
commit is greater than the static wakeup calculated when panel has
large prefill lines(vbp + vpw + vfp) causing janks on primary when
secondary display enters idle and primary display is running. Add changes
to use default_prefill_lines for configuring static wakeup during bootup
when rsc is in clk state. For vid state only, panel prefill
lines will be taken into account for rsc static wakeup calculation.

Change-Id: I3c0ceec984b24b81e3e4d0341f25cdd28f178925
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
2021-08-31 17:48:19 +05:30
qctecmdr
433e1f67b4 Merge "disp: msm: sde: add checks to avoid null pointer dereference" 2021-08-31 01:42:54 -07:00
Yashwanth
9021984e14 disp: msm: sde: add checks to avoid null pointer dereference
This change adds required checks to avoid accessing the
null pointer in case where memory allocation fails while
dumping the registers in memory.

Change-Id: Ic087a1bd041d193820289672d325a78795c48c14
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-08-30 12:01:14 +05:30
qctecmdr
8c8660fcda Merge "disp: msm: assign aspace to gem object for mmap buffer" 2021-08-19 23:46:20 -07:00
qctecmdr
16b3d11221 Merge "disp: msm: sde: remove idle time from Qsync threshold calculation" 2021-08-19 23:46:19 -07:00
Yashwanth
d7d8a487ca disp: msm: assign aspace to gem object for mmap buffer
During gem fault, if aspace value is found to be NULL
pages map request will be failed. This change assigns
nonsecure aspace to gem object before mapping the pages
in such cases.

Change-Id: Ia838fd8a446e21771742ec9d51e30fe08c989e6e
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-08-19 10:45:46 +05:30
qctecmdr
a85df97b3a Merge "disp: pll: Fix cfg1 value when pclk_src_mux parent is updated" 2021-08-17 01:43:27 -07:00
qctecmdr
b7747c3d23 Merge "disp: msm: sde: hold vmlock only during transition in check phase" 2021-08-13 05:10:34 -07:00
Ritesh Kumar
272f660e76 disp: pll: Fix cfg1 value when pclk_src_mux parent is updated
Currently, PLL_CFG1(1:0) register is updated with cached values
in dsi_pll_enable. This can create issue when UEFI and kernel
cfg1 programming is not same. To fix it, return cached value
of cfg1 when its read in pclk_mux_read, so that pclk_mux_write
is called and cached value is updated. This fix is for 10nm pll.

Change-Id: I8465cb9027a1639f3cdeb02274513ac680f84632
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-08-12 04:08:13 -07:00
Steve Cohen
77d385f62d disp: msm: sde: remove idle time from Qsync threshold calculation
Remove idle time from the Qsync calculation, round down to
the nearest multiple of 4 and remove a couple of extra lines
to compensate for possible latencies. This helps to reduce
the possibility of causing tearing due to the driver calculation
mismatching with the DDIC's expected timeout value.

Change-Id: I8a53a989e26cbd7f0e2b94caa8df8f5bee3ad26c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-11 22:38:04 -07:00
Veera Sundaram Sankaran
2a15e531a3 disp: msm: fix dsi debugbus in-mem logging
Update the dump_mem pointer offset while storing the debugbus
data for the second DSI to avoid overwriting to same memory.
As part of the change, register the DSI ctrl with sde_dbg from
ctrl_init directly, instead of debugfs_init to avoid code replication.

Change-Id: I4089f3038ffa89136eaea956d27270f638a99043
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-08-10 16:02:55 +05:30
Veera Sundaram Sankaran
b8a5bf949a disp: msm: add capability to dump limited debugbus info in logs
Add a flag SDE_DBG_DUMP_IN_LOG_LIMITED based on which the debug bus
registers dumped in log can be limited. In memory logging will continue
to dump the full range of configured registers if that flag is set.
Currently the in-log limited support is enabled  only for the sde/vbif
debugbus and both IN_LOG & IN_LOG_LIMITED will be treated the same way
for other blocks.

Change-Id: Ie85d3d16955cfa507bb3e02954d9b313851eef78
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-08-10 15:37:16 +05:30
Andhavarapu Karthik
75fa44a8ab disp: msm: format register/debugbus dumping in logs
Add macros for logging the registers/debugbus, so all blocks
can use the same macros to keep the log format consistent.

Change-Id: Ie28ce83a742f24f3091bedab66c8cf1454bbb943
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-08-10 15:28:46 +05:30
Andhavarapu Karthik
afafffe4ac disp: msm: refactor debugbus to use same helpers
Refactor the debugbus read/logging for sde/dsi/vbif/lutdma to use the
same helpers. Use function pointers to read/write specific hw block
operations. Remove the DBGBUS_FLAGS_DSPP and related checks  as it is
not used. Increase the debugbus block/test-point ranges for all the
blocks to log all the test-points used by hardware.

Change-Id: I07b23d21f9c556eb7575b892f87ab94adfe41116
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-08-10 15:10:06 +05:30
Yashwanth
d7ae274eeb disp: msm: sde: hold vmlock only during transition in check phase
In the current code, vmlock is always acquired in check
phase even if there is no transition between vm's. This
might result in janks if vmlock is held concurrently by
other processes such as backlight update. This change
ensures that vmlock is held only if there is a valid
transition request between vm's in check phase.

Change-Id: I022f04c19ba04fdd5494580cc1436747620b9354
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-08-10 10:24:59 +05:30
qctecmdr
043cd065b3 Merge "disp: msm: sde: increase max size of KMS_INFO" 2021-07-29 21:32:35 -07:00
qctecmdr
75c310ae3e Merge "disp: msm: sde: skip RM reserve for primary in cwb on/off usecase" 2021-07-29 21:32:35 -07:00