Commit Graph

65616 Commits

Author SHA1 Message Date
Grant Likely
31e8d4603e [POWERPC] XilinxFB: add of_platform bus binding
Adds the of_platform bus binding to the xilinxfb driver.  Needed to
use framebuffer devices described in the OF device tree (used by
arch/powerpc).

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Andrei Konovalov <akonovalov@ru.mvista.com>
2007-10-09 18:12:02 -06:00
Grant Likely
47473e3158 [POWERPC] XilinxFB: cleanup platform_bus binding to use platform bus API.
Change the platform bus binding to make use of the established
platform_bus API.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Andrei Konovalov <akonovalov@ru.mvista.com>
2007-10-09 18:11:50 -06:00
Grant Likely
264776224d [POWERPC] XilinxFB: Split device setup from bus binding
Split the device setup code away from the platform bus binding.  This is
in preparation for adding the of_platform bus binding to this driver and
most of the setup code is common between the two busses.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Andrei Konovalov <akonovalov@ru.mvista.com>
2007-10-09 18:11:40 -06:00
Grant Likely
3fb99ce4e2 [POWERPC] XilinxFB: rename failout labels to reflect failure
Labels and gotos are used in xilinxfb_assign to unwind allocations
on device registration failures.  Rename the labels to reflect the
error which occured.  This change is being made to make it easier
to add new failout paths (which occurs in a subsuquent patch) and
to make reviewing the failout path easier.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Andrei Konovalov <akonovalov@ru.mvista.com>
2007-10-09 18:11:29 -06:00
Grant Likely
3cb3ec2c26 [POWERPC] XilinxFB: Replace calls to printk with dev_dbg, dev_err, etc.
The dev_dbg, dev_err, etc functions provide more context that plain
vanilla printk which is useful for debugging.  Where appropriate,
change printk calls to the appropriate dev_*() call.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Andrei Konovalov <akonovalov@ru.mvista.com>
2007-10-09 18:11:20 -06:00
Grant Likely
258de4badd [POWERPC] XilinxFB: add banner output to probe routine when DEBUG is defined
Debug support: when DEBUG is defined, output relevant details to the
log about the framebuffer registration.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Andrei Konovalov <akonovalov@ru.mvista.com>
2007-10-09 18:11:07 -06:00
Grant Likely
dcccb37e98 [POWERPC] Lite5200: Use comma delimiter format for lists in device tree
DTC now supports "foo","bar" format for lists of strings; use the new
format on the lite5200 device trees.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 13:31:41 -05:00
Peter Korsgaard
082ea86fce [POWERPC] spi: Support non-QE processors
On non-QE processors (mpc831x/mpc834x) the SPI clock is the SoC clock.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 09:05:30 -05:00
Anton Vorontsov
803dedb608 [POWERPC] 85xx: mpc85xx_mds - reset UCC ethernet properly
Apart from that the current code doesn't compile it's also
meaningless with regard to the MPC8568E-MDS' BCSR.

This patch used to reset UCCs properly.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:39:07 -05:00
Anton Vorontsov
af6521ea8a [POWERPC] 85xx: mpc8568mds - update dts to be able to use UCCs
1. UCC1's RX_DV pin is 16, not 15;
2. UCC1's phy is at 0x7, not 0x1. Schematics says 0x7, and recent
   u-boot also using 0x7.
3. Use gianfar's (eTSEC) mdio bus. This is hardware default setup.
4. tx-clock should be CLK16 (GE125, PB31);
5. phy-connection-type is RGMII-ID;

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:39:04 -05:00
Anton Vorontsov
321872dcc0 [POWERPC] QE: pario - support for MPC85xx layout
8 bytes padding required to match MPC85xx registers layout.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:39:01 -05:00
Anton Vorontsov
cccd21027c [POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading
set_irq_chained_handler overwrites MPIC's handle_irq function
(handle_fasteoi_irq) thus MPIC never gets eoi event from the
cascaded IRQ. This situation hangs MPIC on MPC8568E.

To solve this problem efficiently, QEIC needs pluggable handlers,
specific to the underlaying interrupt controller.

Patch extends qe_ic_init() function to accept low and high interrupt
handlers. To avoid #ifdefs, stack of interrupt handlers specified in
the header file and functions are marked 'static inline', thus
handlers are compiled-in only if actually used (in the board file).
Another option would be to lookup for parent controller and
automatically detect handlers (will waste text size because of
never used handlers, so this option abolished).

qe_ic_init() also changed in regard to support multiplexed high/low
lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic()
handler implemented appropriately.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:57 -05:00
Anton Vorontsov
55f9ed0f6a [POWERPC] mpc85xx_mds: select QUICC_ENGINE
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:54 -05:00
Timur Tabi
090fe850f9 [POWERPC] 86xx: update immap_86xx.h for the 8610
Update the definition of the global utilities structure (ccsr_guts) in
immap_86xx.h and add some related macros for the Freescale 8610 SOC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:50 -05:00
Kumar Gala
e1c1575f83 [POWERPC] 85xx/86xx: refactor RSTCR reset code
On the majority of 85xx & 86xx we have a register that's ability to
assert HRESET_REQ to reset the board.  We refactored that code so it
can be shared between both platforms into fsl_soc.c and removed all
the duplication in each platform directory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:47 -05:00
Kumar Gala
c9438affcb [POWERPC] Use for_each_ matching routinues for pci PHBs
On the Freescale embedded (83xx, 85xx, 86xx) and a few of the discrete
bridges (mpc10x, tsi108) use the new for_each_compatible_node() or
for_each_node_by_type() to provide more exact matching when looking for
PHBs in the device tree.

With the previous code it was possible to match on pci bridges since
we were only matching on device_type.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:40 -05:00
Kumar Gala
2fce1225af [POWERPC] FSL: Access PCIe LTSSM register with correct size
The LTSSM register is actual 32-bits wide so we should be doing a
dword access.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:37 -05:00
Dale Farnsworth
873553b3d6 [POWERPC] 85xx: Failure with odd memory sizes and CONFIG_HIGHMEM
The CONFIG_FSL_BOOKE mmu setup code fails when CONFIG_HIGHMEM=y
and the 3 fixed TLB entries cannot exactly map the lowmem size.
Each TLB entry can map 4MB, 16MB, 64MB or 256MB, so the failure
is observed when the kernel lowmem size is not equal to the
sum of up to 3 of those values.

Normally, memory is sized in nice numbers, but I observed this
problem while testing a crash dump kernel.  The failure can
also be observed by artificially reducing the kernel's main
memory via the mem= kernel command line parameter.

This commit fixes the problem by setting __initial_memory_limit
in adjust_total_lowmem().

Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:34 -05:00
Xianghua Xiao
0e65bfe34c [POWERPC] Add initial MPC8610 HPCD Platform files.
Add basic board support for the MPC8610 HPCD.  This does
not include any support the SoC Display or Audio controllers.

Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loelier <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:31 -05:00
Jason Jin
61c5d3cde1 [POWERPC] Treat 8610 PCIe host bridge as transparent
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:26 -05:00
Xianghua Xiao
53f3945a16 [POWERPC] Add initial MPC8610 HPCD Device Tree Source file.
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:23 -05:00
Peter Korsgaard
f023dc769c [POWERPC] spi: mode should be "cpu-qe" instead of "qe"
Mode should be "cpu-qe" for QE in CPU mode. "qe" should be reserved
for native QE mode.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:20 -05:00
Peter Korsgaard
33799e3379 [POWERPC] spi: Use fsl_spi instead of mpc83xx_spi
According to booting-without-of.txt, compatible should be "fsl_spi" and
mode "cpu" or "qe" for the fsl SPI controllers.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:17 -05:00
Timur Tabi
6b0b594bb8 [POWERPC] qe: miscellaneous code improvements and fixes to the QE library
This patch makes numerous miscellaneous code improvements to the QE library.

1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type()
   (every caller of ucc_init_guemr() also calls ucc_set_type()).  Modify all
   callers of ucc_set_type() accordingly.

2. Remove the unused enum ucc_pram_initial_offset.

3. Refactor qe_setbrg(), also implement work-around for errata QE_General4.

4. Several printk() calls were missing the terminating \n.

5. Add __iomem where needed, and change u16 to __be16 and u32 to __be32 where
   appropriate.

6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed
   with the wrong value.

7. Add the protocol type to struct us_info and updated ucc_slow_init() to
   use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED.

8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx()

9. Add several macros in qe.h (mostly for slow UCC support, but also to
   standardize some naming convention) and remove several unused macros.

10. Update ucc_geth.c to use the new macros.

11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol
    to use when initializing the UCC in ucc_slow_init().

12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since
    these are the real names of the registers.

13. Use the setbits, clrbits, and clrsetbits where appropriate.

14. Refactor ucc_set_qe_mux_rxtx().

15. Remove all instances of 'volatile'.

16. Simplify get_cmxucr_reg();

17. Replace qe_mux.cmxucrX with qe_mux.cmxucr[].

18. Updated struct ucc_geth because struct ucc_fast is not padded any more.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:15 -05:00
Kumar Gala
6039680705 [POWERPC] Update .gitignore for new vdso generated files
We now generate vdso[32,64].so.dbg as part of the build so
add them to .gitignore

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:38:12 -05:00
Kumar Gala
86a04d9c85 [POWERPC] Fixup MPC8568 dts
The PCI nodes on the MPC8568 dts didn't get moved up to be sibilings of the
SOC node when we did that clean up for some reason.  Fix that up and some
minor whitespace and adjusting the size of the soc reg property.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-08 08:37:58 -05:00
Anton Vorontsov
6b9c67681b [POWERPC] mpc8568mds.dts: fix PCIe I/O address space location and size
According to u-boot/board/mpc8568mds/init.S:

LAW(Local Access Window) configuration:
2)   0xa000_0000   0xbfff_ffff     PCIe MEM                512MB
4)   0xe280_0000   0xe2ff_ffff     PCIe I/O                8M

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 15:47:28 -05:00
Anton Vorontsov
c0e4eb2d8a [POWERPC] MPC8568E-MDS: add support for ds1374 rtc
MPC8568E-MDS have DS1374 chip on the I2C bus, thus let's use it.
This patch also adds #address-cells and #size-cells to the I2C
controllers nodes.

p.s. DS1374 rtc class driver is in the -mm tree, its name is
rtc-rtc-class-driver-for-the-ds1374.patch.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 15:47:25 -05:00
Anton Vorontsov
da1bb3a0e1 [POWERPC] fsl_soc: fix uninitialized i2c_board_info structure
i2c_board_info used semi-initialized, causing garbage in the
info->flags, and that, in turn, causes various symptoms of i2c
malfunctioning, like PEC mismatches.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 15:47:23 -05:00
Scott Wood
15f8c604a7 [POWERPC] cpm: Describe multi-user ram in its own device node.
The way the current CPM binding describes available multi-user (a.k.a.
dual-ported) RAM doesn't work well when there are multiple free regions,
and it doesn't work at all if the region doesn't begin at the start of
the muram area (as the hardware needs to be programmed with offsets into
this area).  The latter situation can happen with SMC UARTs on CPM2, as its
parameter RAM is relocatable, u-boot puts it at zero, and the kernel doesn't
support moving it.

It is now described with a muram node, similar to QE.  The current CPM
binding is sufficiently recent (i.e. never appeared in an official release)
that compatibility with existing device trees is not an issue.

The code supporting the new binding is shared between cpm1 and cpm2, rather
than remain separated.  QE should be able to use this code as well, once
minor fixes are made to its device trees.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 15:47:05 -05:00
Kumar Gala
3c5df5c26e [POWERPC] Cleaned up whitespace in head_fsl_booke.S
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:03:06 -05:00
Emil Medve
b6927bca24 [POWERPC] QE: Added missing CEURNR register
According to the publicly available MPC8360E RM (rev. 1 from 09/2006 and rev. 2
from 05/2007) and MPC8323E RM (rev. 1 from 09/2006), CEURNR is the QE microcode
revision number register and is located at offset 0x1b8 within the QE internal
register space

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:03:03 -05:00
Peter Korsgaard
0438c28fa4 [POWERPC] fsl_soc: rtc-ds1307 support
Add support for the I2C devices handled by the rtc-ds1307 driver to
of_register_i2c_devices.

Cc: G. Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:03:00 -05:00
Peter Korsgaard
210805e219 [POWERPC] fsl_soc: Fix trivial printk typo.
Fix a trivial printk typo in fsl_soc.

Cc: G. Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:57 -05:00
Scott Wood
5dd57a1308 [POWERPC] 8xx: Move softemu8xx.c from arch/ppc
Previously, Soft_emulate_8xx was called with no implementation, resulting in
build failures whenever building 8xx without math emulation.  The
implementation is copied from arch/ppc to resolve this issue.

However, this sort of minimal emulation is not a very good idea other than
for compatibility with existing userspaces, as it's less efficient than
soft-float and can mislead users into believing they have soft-float.  Thus,
it is made a configurable option, off by default.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:54 -05:00
Roy Zang
c4e05bc57d [POWERPC] bootwrapper: adds cuboot for MPC7448HPC2 platform
This patch adds cuboot support for MPC7448HPC2 platform.
The cuImage can be used with legacy u-boot without FDT support.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:50 -05:00
Scott Wood
3611f2ad42 [POWERPC] mpc82xx: Add pq2fads board support.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:47 -05:00
Scott Wood
e00c5498a2 [POWERPC] mpc82xx: Update mpc8272ads, and factor out PCI and reset.
1. PCI and reset are factored out into pq2.c.  I renamed them from m82xx
to pq2 because they won't work on the Integrated Host Processor line of
82xx chips (i.e. 8240, 8245, and such).

2. The PCI PIC, which is nominally board-specific, is used on multiple
boards, and thus is used into pq2ads-pci-pic.c.

3. The new CPM binding is used.

4. General cleanup.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:44 -05:00
Scott Wood
11c146cc19 [POWERPC] 8xx/wrapper: Embedded Planet EP88xC support
This board is also resold by Freescale under the names
"QUICCStart MPC885 Evaluation System" and "CWH-PPC-885XN-VE".

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:40 -05:00
Scott Wood
20906ecea2 [POWERPC] 8xx: mpc885ads cleanup
It now uses the new CPM binding and the generic pin/clock functions, and
has assorted fixes and cleanup.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:38 -05:00
Scott Wood
96fca1dea8 [POWERPC] Document local bus nodes in the device tree, and update cuboot-pq2.
The localbus node is used to describe devices that are connected via a chip
select or similar mechanism.  The advantages over placing the devices under
the root node are that it can be probed without probing other random things
under the root, and that the description of which chip select a given device
uses can be used to set up mappings if the firmware failed to do so in a
useful manner.

cuboot-pq2 is updated to match the binding; previously, it called itself
chipselect rather than localbus, and used phandle linkage between the
actual bus node and the control node (the current agreement is to simply use
the fully-qualified address of the control registers, and ignore the overlap
with the IMMR node).

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:34 -05:00
Scott Wood
2d2294ae12 [POWERPC] mpc8272ads: Change references from 82xx_ADS to 8272_ADS.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:31 -05:00
Scott Wood
d1df447197 [POWERPC] mpc82xx: Rename mpc82xx_ads to mpc8272_ads.
This is just a rename patch; internal references to mpc82xx_ads will be
changed in the next one.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:27 -05:00
Scott Wood
4ff62e1c7f [POWERPC] mpc82xx: Remove a bunch of cruft that duplicates generic functionality.
m82xx_calibrate_decr(), mpc82xx_ads_show_cpuinfo(), and mpc82xx_halt() do
anything useful beyond what the generic code does.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:24 -05:00
Scott Wood
11af1192b7 [POWERPC] mpc82xx: Define CPU_FTR_NEED_COHERENT
The 8272 (and presumably other PCI PQ2 chips) appear to have the
same issue as the 83xx regarding PCI streaming DMA.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:21 -05:00
Scott Wood
7f21f52940 [POWERPC] cpm2: Add cpm2_set_pin().
This provides a generic way for board code to set up CPM pins, rather
than directly poking magic values into registers.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:18 -05:00
Scott Wood
2652d4ec4a [POWERPC] cpm2: Add SCCs to cpm2_clk_setup(), and cpm2_smc_clk_setup().
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:14 -05:00
Scott Wood
449012daa9 [POWERPC] cpm2: Infrastructure code cleanup.
Mostly sparse fixes (__iomem annotations, etc); also, cpm2_immr
is used rather than creating many temporary mappings.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-04 11:02:04 -05:00
John Traill
544cdabe64 [POWERPC] 8xx: Set initial memory limit.
The 8xx can only support a max of 8M during early boot (it seems a lot of
8xx boards only have 8M so the bug was never triggered), but the early
allocator isn't aware of this.  The following change makes it able to run
with larger memory.

Signed-off-by: John Traill <john.traill@freescale.com>
Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-03 20:36:36 -05:00
Scott Wood
7401685242 [POWERPC] 8xx: Work around CPU15 erratum.
The CPU15 erratum on MPC8xx chips can cause incorrect code execution
under certain circumstances, where there is a conditional or indirect
branch in the last word of a page, with a target in the last cache line
of the next page.  This patch implements one of the suggested
workarounds, by forcing a TLB miss whenever execution crosses a page
boundary.  This is done by invalidating the pages before and after the
one being loaded into the TLB in the ITLB miss handler.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-03 20:36:36 -05:00