Since the VSVDB parsing has been moved to the sde edid parser, replace
the usage of drm_connector with sde_connector for hdr10+ so that the
modifications to drm_connector can be removed.
Change-Id: I7d69aa533e71fa45bfc578db24c17bb23e499c4a
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add VSVDB parsing support to sde edid parser. This is required
for HDR10+ support. Currently the parsing is done in the upstream
edid parser. This shall be removed in a subsequent change.
Change-Id: Ibd3a31e12bba68e14e278e0e478656453eb111ac
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
DPU configuration should be changed when resolution switch happens at
the layer mixer level for ltm feature. Driver should mark ltm properties
as dirty when resolution switch happens. Change handles dynamic resolution
switch for ltm by marking the properties as dirty.
Change-Id: I5ffc8e74c42da6c2902eb42fd2e3ed1b9f9e3e4c
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Add support for hardware based rounded corner part of
color processing framework.
Change-Id: I3e5f4dac6ffc759bb940215b7621ac716f255169
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Use the new helpers for parsing DSPP device nodes entries.
Change-Id: I620ba80cac90f34faa1f853f00cf856370ae387c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Simplify device node parsing by using a new structure for
temporarily holding the read properties and create helpers for
getting/freeing all the properties in a sde_prop_type table.
This patch uses these helpers for CTL and mixer parsing,
other blocks will be refactored as well.
Change-Id: I546f32baea8fc09c36a7f24b042f1f1615770b72
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This changes swaps the order of encode initialization between
wb and dsi displays. This ensures that wb encoder is registered
before DSI/DP encoder in mode_list and it allows single CRTC
to loop through WB encoder before other encoder during mirror mode
topology like CWB use case. With existing order of encoder list, CWB
flush is happening after primary commit flush which is causing cwb
failures when there is a cpu latency.
Change-Id: I24d6b4f27271d46e9743d17a624ac7e0930f7474
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This change updates the block offsets for concurrent writeback
blocks and fixes the register dumping logic.
Change-Id: I41b540773fea60e66cab5d476dff1a19b4f4b3db
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This change fixes issues which causes corruption for dual dsi
dsc panel. It fixes the number of slices configured on
dsc hw block and handles deriving correct picture width from
mode timings. Additionally it fixes the core max buffer sizes
used by the hw block.
Change-Id: Iec0ef80528425ffcb5f29d469bd181eb7040de16
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Set the prop_count corresponding to unsigned 32-bit integers and
boolean types to 1. With this change prop_count should have a
positive value for all properties which exist under the device node.
Change-Id: I601870dc25ab347b742fcc4aa2f6bea2397c6caf
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add changes to commit and decrement only those
hardware resources which are required for the modeset.
Timeline of Commit C1 with CWB modeset:
---> Atomic_check
Primary encoder has allocated required HW resources.
CWB encoder has allocated required HW resources.
---> Atomic_commit
On primary encoder, connector is seamless hence
there is no virt_modeset call.
On CWB encoder, there is virt_mode_set call
and during commit HW blocks there is unconditional
decrement for all the HW blocks with rsvp_nxt.
This change ensures hardware blocks are available during
dp display mode validations.
Change-Id: Ifd9439cfc96e727c3093af5f47802c8367775cd7
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
Avoid corrupting the cb_list by setting timestamp before signal.
The fence driver changed in msm-5.4 by creating a union for the
fence cb_list, timestamp, and rcu. Therefore only one of these
fields can be used at a time. Fence driver will take care of
setting the timestamp during dma_fence_signal after it has
cached the cb_list. Also, use fence framework API to set fence
error instead of modifying the dma_fence struct directly.
Change-Id: I58dbaa495027cb575f4f0b03275ca4aa551ecacb
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Avoid exposing any uninitialized data when setting up the
interrupt tables.
Change-Id: I00d3dc8b5acc843401148585a129fde58e326beb
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change programs dither based on user mode input data and
reprograms the dither when device comes out of power collapse.
Change-Id: I83be20c8eb2dc2221cc57cd2395f6512338ff6ef
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Update the definition of the atomic_check function for
DisplayPort connectors to align with the DRM upstream changes.
Change-Id: Id942c8ef16ae773540c4bc7221e0b784354a527c
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update sde_drm.h header to use the display techpack path for
kernel-5.4.
Change-Id: I2b7dcbbde8128eece7a2a8a652f9f7c427b38110
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Fix and decouple widebus-enable flag from dsc_en for dp.
Change-Id: I2d31bc367f007d4c918babc1c051492544bbb05c
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update the mode validation logic by halving the mode clock
when widebus is enabled.
Change-Id: I8f060d8b60403aa5020496983bec0b3e2878b08b
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
When DP is working in MST mode, reading native EDID from MST
branch is not a valid operation.
Change-Id: I297d2b25b2c3166d68ef3eba941ca787d8bce8d3
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
In the current kernel version calling kthread_mod_delayed_work
in irq context is not allowed. Due to this resource control state
change to idle on frame done is handled in display thread context.
Change-Id: I709f7e04ac23d7dde72cea1c19d3767b6abc147e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
The original SB DMA last command logic results in multi
feature sets being applied across different frames. Update
the SB DMA logic to do a single last command per CTL path
to ensure all features using SB DMA can get applied in the
same frame.
Change-Id: Ida837765c0f018b0e03afb0a33ece625a0df81eb
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
The current implementation of DSPP GAMUT + IGC programming rely on
SBDMA for programming. This will cause GAMUT + IGC to be
unprogrammable on derivative Lahaina chipsets that do not have SBDMA
support.
Update the SBDMA handling to more intelligently check if SBDMA is
present, and fallback to DBDMA module where possible.
Change-Id: I89d07e38459ab59b96c69558178b8e97062ed93d
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
A new LUTDMA opcode is added to LUTDMA V2 to speed up certain LUT
programming. This change updates the SSPP Gamut LUT programming using
the new opcode and new LUT BUS.
Change-Id: I8b88483dc3acbfcdbd6f441bc2105f4368fa42bb
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Add new implementation for DSPP GAMUT and IGC features using
newly added SB LUTDMA.
Change-Id: Iebc099351fde058d7f0e20a9e256bcd71c557506
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
A new LUTDMA HW instance has been added to support programming of
SB features via LUTDMA. This change adds corresponding support for
the new SB LUTDMA, including catalog parsing, reg_dma init/deinit/ops
updates and new opcode support.
Change-Id: I0fed7a6e93cd96fe9fe562d2470a8789b161d1bc
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Extend unified flush bit support to control new DSPP
SB LUTDMA bit.
Change-Id: Iba941a4bcd140ceb88e49ab83700c4baef804e0f
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Remove colorspace property from connector until upstream
changes are merged and we can validate the related features.
This change is required to enable DP bring up activities.
Change-Id: I6c1af61732e572b2ffd16e0a323d08154aa83b53
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
In atomic test phase DSC Hw block should be allowed to be reserved
without checking the mode information. Mode information is not
available before bridge enable is called and this results into dsc
not programmed very first mode set.
Change-Id: Ia9ec9a3c9387e34a8bb1d98ee6932aef8725bc8c
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Reduce the cyclomatic complexity for installing CRTC properties.
Change-Id: I42572413713b3a079fb5edcaa25d9050b76adc6c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The clock framework nulls the clock hardware init data, after a variant
of clk_register is called on the clk_hw pointer. This results in a null
pointer dereference when we try to call set rate in the PLL prepare
function. The call can be a direct call to the function rather than
trying to access through the init_data pointer of the clk_hw.
Change-Id: I3613eea915d4f5620d7f0258ae391ad2ac624148
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
