The original SB DMA last command logic results in multi
feature sets being applied across different frames. Update
the SB DMA logic to do a single last command per CTL path
to ensure all features using SB DMA can get applied in the
same frame.
Change-Id: Ida837765c0f018b0e03afb0a33ece625a0df81eb
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
The current implementation of DSPP GAMUT + IGC programming rely on
SBDMA for programming. This will cause GAMUT + IGC to be
unprogrammable on derivative Lahaina chipsets that do not have SBDMA
support.
Update the SBDMA handling to more intelligently check if SBDMA is
present, and fallback to DBDMA module where possible.
Change-Id: I89d07e38459ab59b96c69558178b8e97062ed93d
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
A new LUTDMA opcode is added to LUTDMA V2 to speed up certain LUT
programming. This change updates the SSPP Gamut LUT programming using
the new opcode and new LUT BUS.
Change-Id: I8b88483dc3acbfcdbd6f441bc2105f4368fa42bb
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Add new implementation for DSPP GAMUT and IGC features using
newly added SB LUTDMA.
Change-Id: Iebc099351fde058d7f0e20a9e256bcd71c557506
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
A new LUTDMA HW instance has been added to support programming of
SB features via LUTDMA. This change adds corresponding support for
the new SB LUTDMA, including catalog parsing, reg_dma init/deinit/ops
updates and new opcode support.
Change-Id: I0fed7a6e93cd96fe9fe562d2470a8789b161d1bc
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Extend unified flush bit support to control new DSPP
SB LUTDMA bit.
Change-Id: Iba941a4bcd140ceb88e49ab83700c4baef804e0f
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Remove colorspace property from connector until upstream
changes are merged and we can validate the related features.
This change is required to enable DP bring up activities.
Change-Id: I6c1af61732e572b2ffd16e0a323d08154aa83b53
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
In atomic test phase DSC Hw block should be allowed to be reserved
without checking the mode information. Mode information is not
available before bridge enable is called and this results into dsc
not programmed very first mode set.
Change-Id: Ia9ec9a3c9387e34a8bb1d98ee6932aef8725bc8c
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Reduce the cyclomatic complexity for installing CRTC properties.
Change-Id: I42572413713b3a079fb5edcaa25d9050b76adc6c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The clock framework nulls the clock hardware init data, after a variant
of clk_register is called on the clk_hw pointer. This results in a null
pointer dereference when we try to call set rate in the PLL prepare
function. The call can be a direct call to the function rather than
trying to access through the init_data pointer of the clk_hw.
Change-Id: I3613eea915d4f5620d7f0258ae391ad2ac624148
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Legacy HW that does not support pre-downscale capability will
incorrectly fail certain scaling checks. Fix those checks to
fully support HW without pre-downscaler.
Change-Id: I8f645bbff959e176c1d4d05a30a580113e320d4b
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The pre-downscale capability is checked in multiple places
within sde_plane.c file. Add a helper function to check this
capability flag instead of manually checking this bit.
Change-Id: I21f818a9d81dd63e5eb3da248532904cfa55c838
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add partial update handling for color processing features.
This will validate and set cp features for each frame if
applicable.
Change-Id: Id78c1f4ecbd74781c0c03c04efb528d6a8b91264
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add atomic check handling in color processing framework.
This will check cp features during the validate phase.
Change-Id: I6d94316a749ad247aec0554c31fa56af6db61ab6
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add support for absolute mdss addressing lutdma payload. This will
allow any mdss register to be programmed using lutdma.
Change-Id: I3af3a85182a75a0583c49c797d6adf99b6ba2ee7
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
This change enables the interface hw block to accept
64-bit compressed pixels. This configuration is enabled based
on hw capability. For current hw, this is required any time
the compressed pixels flow through the interface block,
whereas in the previous version of DPU hw this configuration
is only required for topology using 4 way dsc merge.
Change-Id: I7bf79d035dba5084c5057022a7fa1117479e8d52
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Defines should always have a single space between #define and
the keyword to allow for searching where these definitions are
located using grep.
Change-Id: I38778e789b12df8a7a22c22dd27152a5ab047405
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Currently the compression ratio is hard-coded to either 2:1 or
3:1 in several places. This is not sufficient for new compression
algorithms as they can support higher compression ratios.
Add support for calculating the compression ratios from the source
and target bpp thereby eliminating hard-coding.
Change-Id: I6383f3d0c781193d0a9ed74df5a95d8e856edb3d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
As overall display driver is moving away from hard-coded compression
ratios, prepare the DP driver for the same by removing the usage of
the compression ratio enum.
Change-Id: I298db7d20baed8afec9f96dff8c7e950702bfec9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add a generic API which calculates the horizontal timings based
on the compression type in case compression is enabled and even
for non-compression cases.
Replace the usage of the DSC macros with this generic API.
Change-Id: Ie9174c20adc51a0be7c9127529d41faa4b473b55
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support to configure the DPU pipeline to support VDC-m
topologies.
Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add hardware register set and programming for VDC-m block.
Change-Id: I60ef27b507284521abdd10bb679a85303475ddc3
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add hardware catalog support for VDC-m block to parse
the register offsets and feature capabilities.
Change-Id: I1bfbc4b6e7e9f34738d49fecdef4b427a0ccded7
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add the support to program DSI compression registers
for VDC-m. These are calculated based on the VDC parameters
and mode information.
Change-Id: I09b163a496842331d5f2a78371f380180b3a15b8
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support for PPS command for VDC-m. This shall be sent from the
encoder to the decoder such that both can produce the same model
state.
Change-Id: Iae48615eab7c91ef7ecc68b84334057de5090364
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support to calculate the parameters needed to configure
the VDC-m encoder. These are also needed to configure the PPS
command which shall be sent to the decoder.
Change-Id: I36db93f7555aee34b5b893e389a7eb88d0e05f68
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support for parsing VDC-m DTSI parameters and also
perform basic validation checks on those.
Change-Id: I4b13cf04b1500c3c801c227658cb787bdad6174f
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This change adds the hooks to enable the active signal override
in power collapse sequence. Active signal override is needed to
disable the clock gating when the power collapse sequence
is running.
Change-Id: I9edaed7960b236b3d0179cb67f9cc2c9b3546c9d
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change adds support for dsc using the 3d mux hw block.
The 3d_mux hw block merges the input from layer mixer before passing to
dsc block for compression.
Change-Id: I21544c33fff2c1e604c0ae712a036a127d25afcf
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Certain sub-blocks need to be enabled disabled dynamically on a
seemless mode switch (for ex. partial update) CWB is another example
where control path interface configuration needs to be dynamically
changed on enable/disable of concurrent writeback. Similarly
3d mux needs to be enabled/disabled for partial update use cases.
This change modfies the current api update_cwb_cfg and makes it
more generic and adds support to enable/disable only the 3d mux.
Change-Id: I5e5a6e78b0599f689cb2f83d0d626a5f392eff6e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change introduces new ctl path api read_active_status to check
if a particular hw block is active or not in the current control path.
This is specially required in continuous splash use case when bootloader
has programmed certain blocks and the kernel driver tries to find
out the same configuration. This is used to ascertain which DSC block
is active in continuous splash case since DSC blocks are not tied to
mixer blocks.
Change-Id: I8dd590aa2dc764bd340727c166e1133ef9ce7af5
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Certain DSC hw blocks only support 444 mode, while others
support both 444 and 422 modes. This change adds support in
resource manager to check the hw resource requirement with
the capability of the block and then reserve the correct
hw resource.
Change-Id: If85beb2f2f25e9eb7f8a8321c94b57878d048369
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
