wr_ptr_irq timeout signifies that the MDP is stuck
on either the current or previous frame. Handle
ctl reset and fence signalling as part of this
timeout handling. This logic would help to recover
the HW faster in case of posted-start.
Change-Id: I09b3d21772df431f9fc4a58b2fd9b4fcac4a7de7
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
SDE RSC does not need to wait for vsync during
dms. It was removed unintentionally with commit
a74d2cf7fa ("disp: msm: add runtime_pm ops
support in drm driver"). However, Panel mode
switch still needs vsync wait based on
recommendation. This change fixes vsync wait
for both cases.
Change-Id: Ic9119132eb15a8c33f3841ba5df2624189d93395
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Add check for plane used as index on accessing
for bytes per pixel value.
Change-Id: I3642f9a57bf2eee7fa0dbf0965bd8497f3911e18
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Add a check to ensure that audio registers are programmed only
when the DP timing engine (audio session) is enabled. This will
reduce the likelihood of un-clocked register access for audio
related operations.
Change-Id: I6fe59cf53dc721b5470ad4cf7d84e8606800a246
CRs-Fixed: 2465406
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Writeback modes are passed from DRM driver client and it may provide
invalid configuration. Add null checks for sde_wb_config provided by
client to avoid null access in subsequent calls.
Change-Id: I0924f8907d98e2ecb891cfc0c09191823d9033e8
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
The dp sink explicitly states the numbers of
slices it can support. When calculating the
number of slices for dsc configuration, ensure
that the sink supports the calculated number of
slices.
If the sink does not support the calculated
number of slices, keep rechecking sink support
for the subsequent slice increment, until we
reach the highest number of slices possible
according to the dp spec. If no compatible
sink slice support is found, do not enable dsc.
CRs-Fixed: 2325207
Change-Id: I485adacd258963cdec9cc52aa041373883ecadc7
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
Changes to incorporate the different clock names for
lito and kona.
Change-Id: I607366f75426a819226aa252819b507dba07109d
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Initialize LTM phase init_h values with single pipe configuration
value for both LTM blocks, so in dual panel use case, the correct
init_h values will be programed for LTM_0 and LTM_1.
As for dual pipe merge configuration, init_h value for LTM_1 will
be overwrite with the correct configuration if merge_en is set.
Change-Id: I8719b217cf7e5677e23c17b3c3f62f4ee23f43e9
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
Add null check for plane state pointer before
dereferencing it.
Change-Id: Ic66efd11a70162ffe65c2137a5f19688314c45a5
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Write to hardware registers should be exposed for only debug
purpose. Hence use CONFIG_DYNAMIC_DEBUG to restrict register
writes only for debug defconfig.
Change-Id: I0b67b46a69920f6620570ace9d4faf732076126d
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
The change adds a check to make sure the length of bytes being
copied don't exceed the size of the destination buffer
causing an overflow.
Change-Id: Ib3ca3705e4179ccda1af11279e96e167baee6a3b
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add configuration data to handle 10bpp 3:1
compression ratio based on hardware recommended
settings.
CRs-Fixed: 2325207
Change-Id: I7086dc235e0063a79c661fa8cee77d4e47e9c826
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
Ensure that the dp dsc peak pxl rate does not
exceed the maximum supported by the sink device.
If the mode's peak pxl rate per slice exceeds the
max, mark the mode as invalid.
CRs-Fixed: 2325207
Change-Id: Ic8904c759b8621c3aff258206599e1994f70e26e
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
The line buffer bit depth is used as part of dp
dsc calculations. Read the max supported line buf
bit depth supported by sink, and use that
restriction as part of the dsc calculations.
CRs-Fixed: 2325207
Change-Id: I4c995acad5f484edd1b438bdbf6c145b2d35ee41
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
As per hardware recommendation, DMA pipe
width is reduced to 2880, while vig
pipewidth is 4096.
Change-Id: I70dbd44b4883f49879686003ba1fe9694434daab
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
Disable double buffer vsync configuration while
enabling clk and cmd state switch sequence. Leaving
this configuration in enable state may cause different
issues for different state switch. Clock state switch
may see a vsync delay for solver disable. Command
state switch may not update the vsync source.
Change-Id: I910fc7e33a20a04b602435020173d85a4ee926d1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
For DSI PHY timing of version 4, adds the missing configuation
of phy_clk_params and updates some extra clock parameters.
The less precision during calculation is fixed, which is caused by
not exactly following PHY timing document.
Change-Id: Ibb75d4d3e5b4a5979ff4a85dba1accf3677a6584
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Remove dividers that are not recommended for DSI DPHY mode
when setting up the clock tree for the DSI pixel clock.
Change-Id: I2563a35ece541c1f5b46c72af7bd2cc79e72a90e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Force a disconnect if the simulation client disables simulation
before disconnecting from the simulated sink. This ensures that
the driver will not erroneously attempt AUX transactions in
subsequent interactions after simulation is disabled.
Change-Id: Ibc581deafe46753c514bccc70ba5c953c8d49bd8
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Report the HDR10+ sink capability and payload data when user-space
reads the "hdr" debugfs node. Also add support for reporting HDR
properties for MST sessions via the new "hdr_mst" debugfs node.
Write support for this node was removed since it updated the
connector state in an inconsistent way, therefore HDR updates must
come from the atomic commit.
Change-Id: I58af4042c1b3198eb78fe413728104071cf50caf
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Branch address offset for TCS sleep/wake has
changed for lito, add changes to support it.
Change-Id: Id938c4c85df17f6709b9533ff737cf5a0186bc09
Signed-off-by: Animesh Kishore <animeshk@codeaurora.org>
