Commit Graph

566 Commits

Author SHA1 Message Date
qctecmdr
e93fd8adfa Merge "msm: vidc: Add control to handle timestamp reorder" 2020-09-28 09:55:29 -07:00
qctecmdr
0fb5c58c90 Merge "msm: vidc: Force nominal for high bitrate decode usecases" 2020-09-28 09:55:29 -07:00
qctecmdr
e53fcca85f Merge "msm: vdec: Do not consider 10bit size for specific video hardware" 2020-09-28 09:55:29 -07:00
qctecmdr
6e6740b2e5 Merge "msm: venc: reject unsupported sessions with VPSS enabled" 2020-09-28 09:55:29 -07:00
Priyanka Gujjula
173068c67f msm: vidc: Add max-image-load caps to holi and shima
Add max-image-load caps as 8k for holi and
16k for shima for all variants.

Change-Id: I5d1483c0e2dc06af61eca4944bc269e36baa6d73
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
2020-09-23 21:38:09 +05:30
Shi Zhongbo
7377b0c454 msm: venc: reject unsupported sessions with VPSS enabled
Reject any sessions with non-multiple 8 of resolution and
rotation/flip is enabled.

Change-Id: Ifac0cc8884461fe8d2502e92481643d9443aa527
Signed-off-by: Shi Zhongbo <zhongbos@codeaurora.org>
2020-09-21 23:03:41 -07:00
Chandrakant I Viraktamath
70a2ee6e3c msm: vidc: Add control to handle timestamp reorder
Add control to enable/disable timestamp reordering
in driver.

Change-Id: I50c3f60bb8af053881073b40c6df0c74f3f0aafb
Signed-off-by: Chandrakant I Viraktamath <civirakt@codeaurora.org>
2020-09-21 19:24:02 +05:30
Chinmay Sawarkar
2efb0193b3 msm: vidc: Force nominal for high bitrate decode usecases
Force the clocks to NOM if bitrate nears or exceeds maximum
supported for VP9 usecases.

Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>

Change-Id: I917b0f6c624837403fd9f1499a68812acb00b568
2020-09-17 22:18:53 -07:00
qctecmdr
3de9db9637 Merge "msm: vidc: cleanup unsupported profile and levels for VP9" 2020-09-17 10:04:47 -07:00
qctecmdr
9cdb05ab74 Merge "msm: vidc: update calculation for BSE LB write for decoder" 2020-09-17 10:04:47 -07:00
qctecmdr
ea32d6bf6b Merge "msm: venc: enable VUI timing for native recorder" 2020-09-17 10:04:47 -07:00
qctecmdr
6f06f41bfe Merge "msm: vidc: Disable timestamp store-fetch logic" 2020-09-17 10:04:47 -07:00
qctecmdr
be45c1081c Merge "msm: vidc: Optimize enc scratch and scratch_2 buffer sizes" 2020-09-17 10:04:47 -07:00
Govindaraj Rajagopal
b03e989d89 msm: vidc: cleanup unsupported profile and levels for VP9
VP9 decoder spec is reduced. So cleaning up unsupported
profiles & levels for VP9.
Supported Profile - 0 & 2
Max supported level - 5.1

Change-Id: I5b131f5bbd3c50aea2949f62ab6b16d51728ba7d
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
2020-09-17 11:39:32 +05:30
Dikshita Agarwal
31f9744ab8 msm: vidc: update calculation for BSE LB write for decoder
For h264 BSE LB write should be half of BSE LB read for decoder.
Update the calculation for the same.

Change-Id: I5ebceff4fa0795eaaf67b569e754d174be4a8146
Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org>
2020-09-17 01:53:42 +05:30
Priyanka Gujjula
5bef15ac09 msm: vidc: Add query support for HEIC caps
Add support to VIDIOC_ENUM_FRAMESIZES for
querying HEIC frame size.

Change-Id: I9ceba027c798e0c0fb7781702ccb2873fc8276ac
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
2020-09-16 18:51:19 +05:30
qctecmdr
39f4bc3665 Merge "msm: vidc: Increase decoder persist_1 buffer size" 2020-09-14 14:14:19 -07:00
Shi Zhongbo
3e7994b2a0 msm: venc: enable VUI timing for native recorder
Enable VUI timing info when using native recorder
by default.

Change-Id: I1edb9d8b9bcd84e06bcd0f52429bda96af5d0de3
Signed-off-by: Shi Zhongbo <zhongbos@codeaurora.org>
2020-09-14 16:40:28 +08:00
Akshay Chandrashekhar Kalghatgi
2f691c151e msm: vidc: Disable timestamp store-fetch logic
Sometimes during sequence change, timestamps may be repeated. This corner
case breaks the TS store-fetch logic. Disabling this logic for secure
decoder sessions.

Change-Id: Ib5c00cc509364ce29b0f69f9b7441edd11b1eef2
Signed-off-by: Akshay Chandrashekhar Kalghatgi <akalghat@codeaurora.org>
2020-09-11 16:52:06 -07:00
qctecmdr
b580a91082 Merge "msm: vidc: Cleanup HFI_CMD_SESSION_SYNC support" 2020-09-11 12:41:38 -07:00
qctecmdr
4d71ce668e Merge "msm: vidc: update iris2 clock calculation" 2020-09-11 12:41:38 -07:00
Mihir Ganu
fecdc2cd76 msm: vidc: Increase decoder persist_1 buffer size
Increase H264/H265 decoder persist_1 buffer size to acommodate
t35 userdata.

Change-Id: Ifb38d32ee0f3e737b3f8e518976511cf727d295f
Signed-off-by: Mihir Ganu <mganu@codeaurora.org>
2020-09-10 17:17:59 -07:00
qctecmdr
9f6ff22e5b Merge "msm: venc: add bitrate boost QP range interface" 2020-09-10 11:05:16 -07:00
Priyanka Gujjula
ad4f5e8670 msm: vidc: Cleanup HFI_CMD_SESSION_SYNC support
HFI_CMD_SESSION_SYNC is used for synchronization
of encode batching between driver and FW.
Currently, encode batching is only between camera
and driver. To FW, it is always regular encode
session without batching. Hence cleaning up the
encode batching HFI's.

Change-Id: I5d493c98a350e36cd8bb85bf9b82d3f8d41451cf
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
2020-09-10 20:38:42 +05:30
Govindaraj Rajagopal
253c43239c msm: vidc: update iris2 clock calculation
As per vperf sheet, VSP FW Overhead factor(1.05) needs
to be applied to both entropy mode CABAC & CAVLC.

Change-Id: I93dc00137e0633ac2a79862c58970ba43b515ad6
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
2020-09-10 18:25:24 +05:30
Vikash Garodia
10cba22262 msm: vdec: Do not consider 10bit size for specific video hardware
Certain video hardware does not have support for hdr. Avoid adding
size for the same for such video hardware.

CRs-Fixed: 2772982
Change-Id: Iceb64dab0d346fb483976dac16fed4888a2f0277
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
2020-09-09 17:21:59 +05:30
Shi Zhongbo
ec74a635f5 msm: venc: add bitrate boost QP range interface
Add bitrate boost QP range interface to
support additional configs for boost QP range.
Boost QP range should only be effective
when bitrate boost is enabled. And, common vendor
extension QP range overwrites boost QP range.

Change-Id: I9b6601cd7e9bbf4326f67b9e0f40788e915040b0
Signed-off-by: Shi Zhongbo <zhongbos@codeaurora.org>
2020-09-07 16:45:06 +08:00
qctecmdr
5ce35308a9 Merge "msm: vidc: shima: Update max profile level caps" 2020-09-04 09:56:45 -07:00
Priyanka Gujjula
541b40c072 msm: vidc: Optimize enc scratch and scratch_2 buffer sizes
Optimize scratch and scratch_2 internal buffer size
calculators for encoder.

Change-Id: Idfaf7df13a427788cbb983a17fc2137be154bce8
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
2020-09-04 20:33:44 +05:30
Priyanka Gujjula
08b43c99a2 msm: vidc: shima: Update max profile level caps
Update level values for ENC and DEC based on
shima caps.

Change-Id: I967b4ef65a59b711815e09e03547b895cc572e39
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
2020-09-03 20:40:16 +05:30
Govindaraj Rajagopal
fcad90b130 msm: vidc: reverse sort allowed_clock_tbl for shima
Clock_table entries are kept as ascending order. So always
highest clk corner is picked from clock_table during clock
calculation. So enable reverse sort for clk table entries
to pick the right corner.

Change-Id: I5adc61368aa15ae69c11a0539dcb05437bf686b4
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
2020-09-03 18:29:14 +05:30
qctecmdr
f2c416e44e Merge "msm-vidc: update bw calculation for ar50LT" 2020-09-01 02:28:46 -07:00
qctecmdr
f22ff30abf Merge "msm: vidc: Update cycle count requirement of B frames." 2020-08-30 12:54:25 -07:00
Priyanka Gujjula
372b7136f5 msm: vidc: Add support for 128x32 alignment of NV12
Introduce new internal driver color format
V4L2_PIX_FMT_NV12_128 and uapi color format
COLOR_FMT_NV12_128 to map with NV12 128x32
alignment. Also, clean up intermediate HAL
color formats.

Change-Id: Ia28d0f422f2777bda865c2fc6c7499cce9dabb54
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
2020-08-29 00:42:28 +05:30
Chinmay Sawarkar
0bca035ef7 msm: vidc: Update cycle count requirement of B frames.
Decoder base cycle requirement of B frames has increased to 80.
Also, updated cycle count requirement for Encoder HIER B usecase.

Change-Id: Iec1bee89be6bb6c18235c2903080025c312bef2d
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>
2020-08-26 11:30:01 -07:00
Dikshita Agarwal
b28387c5c4 msm-vidc: update bw calculation for ar50LT
Update bw calculation formulas for ar50LT.

Change-Id: Ife2342304947f4108f908f7a5c56de24ad088b23
Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org>
2020-08-24 13:31:17 +05:30
Priyanka Gujjula
2686a86b94 msm: vidc: Include uapi header files from techpack
Currently uapi header files are included from core
kernel include path since core kernel makefile also
includes them. Hence making changes to include path
in techpack makefile such that uapi header files are
included from techpack project.

Change-Id: I604b8bbb3058473b3e301cbbce112c8c93a0e963
Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
2020-08-19 22:32:19 +05:30
qctecmdr
3bf4f90efb Merge "msm: vidc: Restrict dynamic low latency for h264 and hevc" 2020-08-19 03:01:35 -07:00
qctecmdr
9354ca4ba5 Merge "msm: vidc: improve heif decoder performance" 2020-08-18 18:38:24 -07:00
Govindaraj Rajagopal
c24265be5c msm: vidc: Update VP9 decoder capabilities for shima
Update VP9 decoder capabilities for shima to be inline
with lahaina.

Change-Id: Ieab73987d92bb093fd06391086935900b5e01768
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
2020-08-18 18:53:35 +05:30
Qiwei Liu
0e570d90fa msm: vidc: improve heif decoder performance
Add V4L2 interface to indicate heif decoder, and use
below configurations to improve performance.
1. Set turbo session
2. Disable DCVS and batch
3. Increase input and output buffer count to 12
4. Modify input buffer size calculation
5. Avoid framerate calc and ts list maintenance
6. Skip setting bse-vpp delay

Change-Id: I9a47a88154238db3ac4285462c6030114546d333
Signed-off-by: Qiwei Liu <qiweil@codeaurora.org>
2020-08-18 11:34:24 +08:00
Vikash Garodia
b560c7a295 msm: vidc: Restrict dynamic low latency for h264 and hevc
In existing approach, dynamic low latency i.e low latency hint
is restricted via specific low latency components in userspace.
This change adds one more checkpoint to ensure that video
firmware is configured for low latency only for desired codecs.

Change-Id: Iad36c3b84ddc3b94033c4bf5f0afdd3a18600111
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
2020-08-18 01:22:20 +05:30
Mihir Ganu
5a5d1b2859 msm: vidc: Update VP9 decoder capabilities
Revise VP9 decoder capabilities and limits to
match the updated Lahaina PRD.

Change-Id: I7a92c88b21e19ab44b43a0c829491f58aa1ce492
Signed-off-by: Mihir Ganu <mganu@codeaurora.org>
2020-08-14 11:31:30 -07:00
qctecmdr
583ad02d81 Merge "msm: vidc: set chroma_qp_offset only for client set cases" 2020-08-13 23:49:45 -07:00
qctecmdr
c9ab640209 Merge "msm: vidc: update vsp_cycle entries for shima" 2020-08-12 17:19:15 -07:00
qctecmdr
6a424bb70f Merge "msm: vidc: Deprecate Mpeg2 secure decode support" 2020-08-12 17:19:15 -07:00
Govindaraj Rajagopal
36d91e66e0 msm: vidc: set chroma_qp_offset only for client set cases
Set chroma_qp_offset hfi to firmware only for client set cases.
Supported value: 0 & -12

If hfi not set, firmware proceeds with its own default value.
10-bit: default: 0
8-bit : default: Adaptive chroma_qp

Change-Id: I40262aae87b2a385c6cd7d60faa19b6adfe8b151
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
2020-08-12 18:56:04 +05:30
Govindaraj Rajagopal
be77d74ff1 msm: vidc: update vsp_cycle entries for shima
Updated VSP base cycle entries for Shima to inline
with vperf.

Change-Id: I26e7a521434765b97cc1a508b714652d14adf2aa
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
2020-08-11 20:21:52 +05:30
qctecmdr
c1ad7b0054 Merge "msm: vidc: revise timestamp data type to s64" 2020-08-10 16:04:35 -07:00
Shi Zhongbo
b1a132ad57 msm: vidc: revise timestamp data type to s64
Revise internal timestamp data type from u64
to s64 in case of negative timestamps.

Change-Id: Ib026d504a08ce5ac67d1d962b671c37637761321
Signed-off-by: Shi Zhongbo <zhongbos@codeaurora.org>
2020-08-10 13:05:17 -07:00