Commit Graph

52 Commits

Author SHA1 Message Date
Russell King
d1964dab60 Merge branches 'arm', 'at91', 'ep93xx', 'iop', 'ks8695', 'misc', 'mxc', 'ns9x', 'orion', 'pxa', 'sa1100', 's3c' and 'sparsemem' into devel 2008-04-19 17:17:25 +01:00
Russell King
28fab1a2fd [ARM] Fix kernel mode preemption
Luc Van Oostenryck reported:

  The code removed by this patch tested the irq_cpustat_t members
  __local_irq_count and __local_bh_count but these fields have
  been removed some time ago:

  http://git.kernel.org/?p=linux/kernel/git/tglx/history.git;a=commitdiff;h=3ab146c93e039dec99fec8d441a8dd046fe510cc

Fix this oversight.

Acked-by:  Bill Gatliff <bgat@billgatliff.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-04-19 11:28:09 +01:00
Paul Brook
cb170a45d6 Linux Thumb-2 support for user-space applications
This patch implements Thumb-2 application support in Linux. Original
implementation by Paul Brook with fixes for VFP and Neon by Catalin
Marinas.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:08 +01:00
Paul Brook
48d7927bdf Add a prefetch abort handler
This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:07 +01:00
Russell King
d0d42df2a4 Merge branches 'at91', 'ep93xx', 'iop', 'kprobes', 'ks8695', 'misc', 'msm', 's3c2410', 'sa1100' and 'vfp' into devel
* at91: (24 commits)
  [ARM] 4615/4: sam926[13]ek buttons updated
  [ARM] 4765/1: [AT91] AT91CAP9A-DK board support
  [ARM] 4764/1: [AT91] AT91CAP9 core support
  [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation
  [ARM] 4761/1: [AT91] Board-support for NEW_LEDs
  [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200
  [ARM] 4759/1: [AT91] Buttons on CSB300
  [ARM] 4758/1: [AT91] LEDs
  [ARM] 4757/1: [AT91] UART initialization
  [ARM] 4756/1: [AT91] Makefile cleanup
  [ARM] 4755/1: [AT91] NAND update
  [ARM] 4754/1: [AT91] SSC library support
  [ARM] 4753/1: [AT91] Use DMA_BIT_MASK
  [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9
  [ARM] 4751/1: [AT91] ISI peripheral on SAM9263
  [ARM] 4750/1: [AT91] STN LCD displays on SAM9261
  [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY
  [ARM] 4646/1: AT91: configurable HZ, default to 128
  [ARM] 4688/1: at91: speed-up irq processing
  [ARM] 4657/1: AT91: Header definition update
  ...

* ep93xx:
  [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations
  [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type
  [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups
  [ARM] 4668/1: ep93xx: implement new GPIO API

* iop:
  [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field
  [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device
  [ARM] 4708/1: iop: update defconfigs for 2.6.24

* kprobes:
  ARM kprobes: let's enable it
  ARM kprobes: special hook for the kprobes breakpoint handler
  ARM kprobes: prevent some functions involved with kprobes from being probed
  ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack
  ARM kprobes: add the kprobes hook to the page fault handler
  ARM kprobes: core code
  ARM kprobes: instruction single-stepping support

* ks8695:
  [ARM] 4603/1: KS8695: debugfs interface to view pin state
  [ARM] 4601/1: KS8695: PCI support

* misc:
  [ARM] remove duplicate includes
  [ARM] CONFIG_DEBUG_STACK_USAGE
  [ARM] 4689/1: small comment wrap fix
  [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix
  [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h
  [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS
  [SERIAL] 21285: Report baud rate back via termios
  [ARM] Remove pointless casts from void pointers,
  [ARM] Misc minor interrupt handler cleanups
  [ARM] Remove at91_lcdc.h
  [ARM] ARRAY_SIZE() cleanup
  [ARM] Update mach-types

* msm:
  [ARM] msm: dma support for MSM7X00A
  [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A)
  [ARM] msm: irq and timer support for ARCH_MSM7X00A
  [ARM] msm: core platform support for ARCH_MSM7X00A

* s3c2410: (33 commits)
  [ARM] 4795/1: S3C244X: Add armclk and setparent call
  [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code
  [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function
  [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S
  [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk
  [ARM] 4790/1: S3C2412: Fix parent selection for msysclk.
  [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values
  [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used.
  [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number
  [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants
  [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers
  [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches
  [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull()
  [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users
  [ARM] 4781/1: S3C24XX: DMA suspend and resume support
  [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX
  [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call
  [ARM] 4778/1: S3C2412: Add armclk and init from DVS state
  [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk
  [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected
  ...

* sa1100:
  [ARM] sa1100: add clock source support

* vfp:
  [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
  [ARM] 4583/1: ARMv7: Add VFPv3 support
  [ARM] 4582/2: Add support for the common VFP subarchitecture
2008-01-28 13:21:21 +00:00
Nicolas Pitre
785d3cd286 ARM kprobes: prevent some functions involved with kprobes from being probed
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-01-26 15:25:17 +00:00
Nicolas Pitre
d30a0c8bf9 ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack
If kprobes installs a breakpoint on a "stmdb sp!, {...}" instruction,
and then single-step it by simulation from the exception context, it will
corrupt the saved regs on the stack from the previous context.

To avoid this, let's add an optional parameter to the svc_entry macro
allowing for a hole to be created on the stack before saving the
interrupted context, and use it in the undef_svc handler when kprobes
is enabled.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-01-26 15:25:17 +00:00
Nicolas Pitre
70b6f2b4af [ARM] 4689/1: small comment wrap fix
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 14:50:05 +00:00
Catalin Marinas
b5872db4a2 [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
This patch enables the use of the Advanced SIMD (NEON) extension on
ARMv7. The NEON technology is a 64/128-bit hybrid SIMD architecture
for accelerating the performance of multimedia and signal processing
applications. The extension shares the registers with the VFP unit and
enabling/disabling and saving/restoring follow the same rules. In
addition, there are instructions that do not have the appropriate CP
number encoded, the checks being made in the call_fpe function.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 14:44:02 +00:00
Nicolas Pitre
d28a170d5b [ARM] 4665/1: fix __und_usr wrt accessing the undefined insn in user space
The ldrt fixup code expects r9 to be set.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-11-26 19:44:02 +00:00
Nicolas Pitre
b49c0f24cf [ARM] 4659/1: remove possibilities for spurious false negative with __kuser_cmpxchg
The ARM __kuser_cmpxchg routine is meant to implement an atomic cmpxchg
in user space.  It however can produce spurious false negative if a
processor exception occurs in the middle of the operation.  Normally
this is not a problem since cmpxchg is typically called in a loop until
it succeeds to implement an atomic increment for example.

Some use cases which don't involve a loop require that the operation be
100% reliable though.  This patch changes the implementation so to
reattempt the operation after an exception has occurred in the critical
section rather than abort it.

Here's a simple program to test the fix (don't use CONFIG_NO_HZ in your
kernel as this depends on a sufficiently high interrupt rate):

	#include <stdio.h>

	typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
	#define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)

	int main()
	{
		int i, x = 0;
		for (i = 0; i < 100000000; i++) {
			int v = x;
			if (__kernel_cmpxchg(v, v+1, &x))
				printf("failed at %d: %d vs %d\n", i, v, x);
		}
		printf("done with %d vs %d\n", i, x);
		return 0;
	}

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-11-26 19:43:58 +00:00
Dan Williams
f80dff9da0 [ARM] 4185/2: entry: introduce get_irqnr_preamble and arch_ret_to_user
get_irqnr_preamble allows machines to take some action before entering the
get_irqnr_and_base loop.  On iop we enable cp6 access.

arch_ret_to_user is added to the userspace return path to allow individual
architectures to take actions, like disabling coprocessor access, before
the final return to userspace.

Per Nicolas Pitre's note, there is no need to cp_wait on the return to user
as the latency to return is sufficient.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-17 15:04:29 +00:00
Russell King
ae0a846e41 [ARM] Move processor_modes[] to .../process.c
bad_mode() currently prints the mode which caused the exception, and
then causes an oops dump to be printed which again displays this
information (since the CPSR in the struct pt_regs is correct.)  This
leads to processor_modes[] being shared between traps.c and process.c
with a local declaration of it.

We can clean this up by moving processor_modes[] to process.c and
removing the duplication, resulting in processor_modes[] becoming
static.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-06 16:46:48 +00:00
Russell King
db6ccbb61c [ARM] Fix kernel-mode undefined instruction aborts
If the kernel attempts to execute a CP1 or CP2 instruction and it
aborts, and a FP emulator is not loaded, we try to return as if to
a user context, instead of the proper kernel context.  Since the
fault came from kernel mode, we must use the kernel return paths.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-06 22:53:48 +00:00
Lennert Buytenhek
afe4b25e7d [ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-03 17:52:22 +00:00
Russell King
7ad1bcb25c [ARM] Add ARM irqtrace support
This adds support for irqtrace for lockdep on ARM.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-20 14:58:35 +01:00
Nicolas Pitre
ba9b5d7637 [ARM] 3746/2: Userspace helpers must be Thumb mode interworkable
Patch from Nicolas Pitre

The userspace helpers in clean/arch/arm/kernel/entry-armv.S are called
directly in/from userspace. They need to cope with being called from
Thumb code.

Patch below uses the bx interworking instruction when
CONFIG_ARM_THUMB=y.

Based on an earlier patch from Paul Brook <paul@codesourcery.com>

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-08-18 17:20:15 +01:00
Linus Torvalds
a8c4c20dfa Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
  [ARM] 3541/2: workaround for PXA27x erratum E7
  [ARM] nommu: provide a way for correct control register value selection
  [ARM] 3705/1: add supersection support to ioremap()
  [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
  [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
  [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
  [ARM] 3703/1: Add help description for ARCH_EP80219
  [ARM] 3678/1: MMC: Make OMAP MMC work
  [ARM] 3677/1: OMAP: Update H2 defconfig
  [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
  [ARM] Add section support to ioremap
  [ARM] Fix sa11x0 SDRAM selection
  [ARM] Set bit 4 on section mappings correctly depending on CPU
  [ARM] 3666/1: TRIZEPS4 [1/5] core
  ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
  ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
  ARM: OMAP: Update dmtimers
  ARM: OMAP: Make clock variables static
  ARM: OMAP: Fix GPMC compilation when DEBUG is defined
  ARM: OMAP: Mux updates for external DMA and GPIO
  ...
2006-07-02 15:04:12 -07:00
Lennert Buytenhek
ae95bfbb2b [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
Patch from Lennert Buytenhek

This patch makes the iWMMXt context switch hook use the generic
thread notifier infrastructure that was recently merged in commit
d6551e884c.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01 19:56:48 +01:00
Jörn Engel
6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
Lennert Buytenhek
c17fad11f3 [ARM] 3370/2: ep93xx: add crunch support
Patch from Lennert Buytenhek

Add the necessary kernel bits for crunch task switching.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:55:01 +01:00
Russell King
d6551e884c [ARM] Add thread_notify infrastructure
Some machine classes need to allow VFP support to be built into the
kernel, but still allow the kernel to run even though VFP isn't
present.  Unfortunately, the kernel hard-codes VFP instructions
into the thread switch, which prevents this being run-time selectable.

Solve this by introducing a notifier which things such as VFP can
hook into to be informed of events which affect the VFP subsystem
(eg, creation and destruction of threads, switches between threads.)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-22 10:24:18 +01:00
Paul Brook
6896eec029 [ARM] 3420/1: Missing clobber in example code
Patch from Paul Brook

The example code in the source documentation for __kernel_dmb
clobbers r0 but doesn't list it the asm clobber list.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28 22:19:29 +01:00
Russell King
5d25ac038a [ARM] Move IRQ enable after coprocessor number decode
Allow the individual coprocessor handlers to decide when to enable
interrupts, rather than unconditionally enabling them.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:05:50 +00:00
Russell King
43cc19816b [ARM] CONFIG_CPU_MPCORE -> CONFIG_CPU_32v6K
CONFIG_CPU_MPCORE has never been a configuration symbol - it should
be CONFIG_CPU_32v6K.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-02-22 21:13:28 +00:00
Nicolas Pitre
5964eae835 [ARM] 3310/1: add a comment about the possible __kuser_cmpxchg transient false
negative

Patch from Nicolas Pitre

The pre ARMv5 implementation can be aborted if an exception occurs in
the middle of it.  Because of that, the ARMv6 implementation doesn't
re-attempt the operation on a failed strex either.  Let's make this
transient nature of such a false positive more explicit in the
definition.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-02-08 21:19:37 +00:00
Nicolas Pitre
49bca4c281 [ARM] 3309/1: disable the pre-ARMv5 NPTL kernel helper in the non MMU case
Patch from Nicolas Pitre

The cmpxchg emulation on pre-ARMv5 relies on user code executed from a
kernel address.  If the operation cannot complete atomically, it is
aborted from the usr_entry macro by clearing the Z flag.  This clearing
of the Z flag is done whenever the user pc is above TASK_SIZE.

However this "pc >= TASK_SIZE" test cannot work in the non MMU case.
Worse: the current code will corrupt the Z flag on every entry to the
kernel.

Let's disable it in the non MMU case for now.  Using NPTL on non MMU
targets needs to be worked out anyway.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-02-08 21:19:37 +00:00
Nicolas Pitre
5e0974459d [ARM] 3271/1: ARM EABI: fix calling of cmpxchg syscall emulation
Patch from Nicolas Pitre

This is kernel provided user space code.

Since a syscall is used, it has to be updated to work with EABI.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-18 22:38:49 +00:00
Nicolas Pitre
2dede2d8e9 [ARM] 3102/1: ARM EABI: stack pointer must be 64-bit aligned after a CPU exception
Patch from Nicolas Pitre

The ARM EABI says that the stack pointer has to be 64-bit aligned for
reasons already mentioned in patch #3101 when calling C functions.

We therefore must verify and adjust sp accordingly when taking an
exception from kernel mode since sp might not necessarily be 64-bit
aligned if the exception occurs in the middle of a kernel function.

If the exception occurs while in user mode then no sp fixup is needed as
long as sizeof(struct pt_regs) as well as any additional syscall data
stack space remain multiples of 8.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-14 16:18:08 +00:00
Hyok S. Choi
afeb90ca08 [ARM] Support register switch in nommu mode
This patch adds register switch support in nommu mode.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-13 21:05:25 +00:00
Russell King
78ff18a412 [ARM] Cleanup ARM includes
arch/arm/kernel/entry-armv.S has contained a comment suggesting
that asm/hardware.h and asm/arch/irqs.h should be moved into the
asm/arch/entry-macro.S include.  So move the includes to these
two files as required.

Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h
includes which use those facilities, and remove asm/io.h from
kernel/process.c.

Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm
and arch/arm/mach-footbridge.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-03 17:39:34 +00:00
Nicolas Pitre
7c612bfd4e [ARM] 3210/1: add missing memory barrier helper for NPTL support
Patch from Nicolas Pitre

Strictly speaking, the NPTL kernel helpers are required for pre ARMv6
only.  They are available on ARMv6+ as well for obvious compatibility
reasons.  However there are cases where extra memory barriers are needed
when using an SMP ARMv6 machine but not on pre-ARMv6.

This patch adds a memory barrier kernel helper that glibc can use as
needed for pre-ARMv6 binaries to be forward compatible with an SMP
kernel on ARMv6, as well as the necessary dmb instructions to the
cmpxchg helper.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Acked-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-12-19 22:20:51 +00:00
Russell King
37ee16ae93 [ARM SMP] Add core ARM support for local timers
Add infrastructure for supporting per-cpu local timers to update
the profiling information and update system time accounting.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-08 19:08:05 +00:00
Nicolas Pitre
b7ec479553 [ARM] 3115/1: small optimizations to exception vector entry code
Patch from Nicolas Pitre

Since we know the value of cpsr on entry, we can replace the bic+orr with
a single eor.  Also remove a possible result delay (at least on XScale).

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-06 14:42:37 +00:00
Nicolas Pitre
f09b997999 [ARM] 3060/1: allow constants found in asm/memory.h to be used in asm code
Patch from Nicolas Pitre

This patch allows for assorted type of cleanups by letting assembly code
use the same set of defines for constant values and avoid duplicated
definitions that might not always be in sync, or that might simply be
confusing due to the different names for the same thing.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-29 21:44:55 +01:00
Russell King
73394322a4 [ARM] Fix context switch with ARMv6 + TLS
We accidentally corrupted the TLS value when clearing out the ARMv6
exclusive monitor.  Avoid doing so.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-09-23 21:49:58 +01:00
Russell King
b876386ee4 [ARM SMP] Clear the exclusive monitor on ARMv6 CPUs on context switch
Ensure that the exclusive monitor is cleared on context switch with
ARMv6 CPUs.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-08-10 14:52:52 +01:00
Russell King
5ab6091db0 Merge with ../linux-2.6-smp 2005-06-18 09:06:59 +01:00
Nicolas Pitre
dcef1f6346 [PATCH] ARM: 2664/2: add support for atomic ops on pre-ARMv6 SMP systems
Patch from Nicolas Pitre

Not that there might be many of them on the planet, but at least RMK
apparently has one.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-06-08 19:00:47 +01:00
Russell King
ccea7a19e5 [PATCH] ARM SMP: Fix vector entry
The current vector entry system does not allow for SMP.  In
order to work around this, we need to eliminate our reliance
on the fixed save areas, which breaks the way we enable
alignment traps.  This patch changes the way we handle the
save areas such that we can have one per CPU.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-31 22:22:32 +01:00
Russell King
49f680ea7b [PATCH] ARM SMP: convert alignment enable
The current vector entry system does not allow for SMP.  In
order to work around this, we need to eliminate our reliance
on the fixed save areas, which breaks the way we enable
alignment traps.  This patch makes the alignment trap enable
code independent of the way we handle the save areas.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-31 18:02:00 +01:00
Russell King
791be9b976 [PATCH] ARM SMP: add IPI support
Add support for inter-processor interrupts to the main IRQ
handling code.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-21 18:16:44 +01:00
Russell King
706fdd9faa [PATCH] ARM SMP: reallocate main IRQ handler code registers
By changing r9 -> r8 and r8 to 'tsk' (r9) we are able to remove
one instruction from the preempt path.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-21 18:15:45 +01:00
Russell King
187a51ad11 [PATCH] ARM SMP: consolidate main IRQ handler code
Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-05-21 18:14:44 +01:00
Nicolas Pitre
41e46d6ab0 [PATCH] ARM: 2665/1: kill warnings in entry-armv.S
Patch from Nicolas Pitre

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-05 23:24:45 +01:00
Nicolas Pitre
4b0e07a556 [PATCH] ARM: 2663/1: straightify TLS register emulation a bit more
Patch from Nicolas Pitre

This better express things, and should cover RMK's weird SMP toys.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-05-05 23:24:45 +01:00
Nicolas Pitre
2d2669b629 [PATCH] ARM: 2651/3: kernel helpers for NPTL support
Patch from Nicolas Pitre

This patch entirely reworks the kernel assistance for NPTL on ARM.
In particular this provides an efficient way to retrieve the TLS
value and perform atomic operations without any instruction emulation
nor special system call.  This even allows for pre ARMv6 binaries to
be forward compatible with SMP systems without any penalty.
The problematic and performance critical operations are performed
through segment of kernel provided user code reachable from user space
at a fixed address in kernel memory.  Those fixed entry points are
within the vector page so we basically get it for free as no extra
memory page is required and nothing else may be mapped at that
location anyway.
This is different from (but doesn't preclude) a full blown VDSO
implementation, however a VDSO would prevent some assembly tricks with
constants that allows for efficient branching to those code segments.
And since those code segments only use a few cycles before returning to
user code, the overhead of a VDSO far call would add a significant
overhead to such minimalistic operations.
The ARM_NR_set_tls syscall also changed number.  This is done for two
reasons:
1) this patch changes the way the TLS value was previously meant to be
   retrieved, therefore we ensure whatever library using the old way
   gets fixed (they only exist in private tree at the moment since the
   NPTL work is still progressing).
2) the previous number was allocated in a range causing an undefined
   instruction trap on kernels not supporting that syscall and it was
   determined that allocating it in a range returning -ENOSYS would be
   much nicer for libraries trying to determine if the feature is
   present or not.

Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-04-29 22:08:33 +01:00
Russell King
bce495d865 [PATCH] ARM: make entry*.S includes more logical
Move common includes to entry-header, and file specific includes
to the relevant file.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:21:02 +01:00
Russell King
acaca3c915 [PATCH] ARM: Remove SVC_MODE definition
SVC_MODE reflects the MODE_SVC definition in asm/ptrace.h.  Use
the asm/ptrace.h definition instead, and remove SVC_MODE.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:19:48 +01:00
Russell King
1ec42c0c97 [PATCH] ARM: Remove argument for disable_irq/enable_irq
Since we do not require a register for these operations, we can
remove this unnecessary argument.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
2005-04-26 15:18:26 +01:00