android_kernel_xiaomi_sm8350/drivers/clk/qcom/vdd-level-holi.h
Taniya Das 1cdfc65d53 clk: qcom: gpucc-blair: Scale both cx and gx rails for gfx3d clock
There is a requirement to scale both CX and GX rails during the gpu core
clock scaling, thus add the corresponding vdd data.

Change-Id: Ib27f4697a84ece1d0d1ce2b5297c03bf8ed955c6
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
2021-12-06 02:06:18 -08:00

49 lines
1.6 KiB
C

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_H
#define __DRIVERS_CLK_QCOM_VDD_LEVEL_H
#include <linux/regulator/consumer.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
enum vdd_levels {
VDD_NONE,
VDD_MIN, /* MIN_SVS */
VDD_LOWER, /* LOW_SVS / SVS2 */
VDD_LOW, /* SVS */
VDD_LOW_L1, /* SVS_L1 */
VDD_NOMINAL, /* NOM */
VDD_NOMINAL_L1, /* NOM L1 */
VDD_HIGH, /* TURBO */
VDD_HIGH_L1, /* TURBO_L1 */
VDD_NUM,
};
static int vdd_corner[] = {
[VDD_NONE] = 0,
[VDD_MIN] = RPM_SMD_REGULATOR_LEVEL_MIN_SVS,
[VDD_LOWER] = RPM_SMD_REGULATOR_LEVEL_LOW_SVS,
[VDD_LOW] = RPM_SMD_REGULATOR_LEVEL_SVS,
[VDD_LOW_L1] = RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,
[VDD_NOMINAL] = RPM_SMD_REGULATOR_LEVEL_NOM,
[VDD_NOMINAL_L1] = RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,
[VDD_HIGH] = RPM_SMD_REGULATOR_LEVEL_TURBO,
[VDD_HIGH_L1] = RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,
};
static int vdd_gx_corner[] = {
0, 0,
RPM_SMD_REGULATOR_LEVEL_MIN_SVS, RPM_SMD_REGULATOR_LEVEL_MIN_SVS,
RPM_SMD_REGULATOR_LEVEL_LOW_SVS, RPM_SMD_REGULATOR_LEVEL_LOW_SVS,
RPM_SMD_REGULATOR_LEVEL_SVS, RPM_SMD_REGULATOR_LEVEL_SVS,
RPM_SMD_REGULATOR_LEVEL_SVS_PLUS, RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,
RPM_SMD_REGULATOR_LEVEL_NOM, RPM_SMD_REGULATOR_LEVEL_NOM,
RPM_SMD_REGULATOR_LEVEL_NOM_PLUS, RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,
RPM_SMD_REGULATOR_LEVEL_TURBO, RPM_SMD_REGULATOR_LEVEL_TURBO,
RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR, RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,
};
#endif