1cdfc65d53
There is a requirement to scale both CX and GX rails during the gpu core clock scaling, thus add the corresponding vdd data. Change-Id: Ib27f4697a84ece1d0d1ce2b5297c03bf8ed955c6 Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
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#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_H
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#define __DRIVERS_CLK_QCOM_VDD_LEVEL_H
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
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enum vdd_levels {
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VDD_NONE,
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VDD_MIN, /* MIN_SVS */
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VDD_LOWER, /* LOW_SVS / SVS2 */
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VDD_LOW, /* SVS */
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VDD_LOW_L1, /* SVS_L1 */
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VDD_NOMINAL, /* NOM */
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VDD_NOMINAL_L1, /* NOM L1 */
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VDD_HIGH, /* TURBO */
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VDD_HIGH_L1, /* TURBO_L1 */
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VDD_NUM,
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};
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static int vdd_corner[] = {
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[VDD_NONE] = 0,
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[VDD_MIN] = RPM_SMD_REGULATOR_LEVEL_MIN_SVS,
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[VDD_LOWER] = RPM_SMD_REGULATOR_LEVEL_LOW_SVS,
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[VDD_LOW] = RPM_SMD_REGULATOR_LEVEL_SVS,
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[VDD_LOW_L1] = RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,
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[VDD_NOMINAL] = RPM_SMD_REGULATOR_LEVEL_NOM,
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[VDD_NOMINAL_L1] = RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,
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[VDD_HIGH] = RPM_SMD_REGULATOR_LEVEL_TURBO,
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[VDD_HIGH_L1] = RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,
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};
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static int vdd_gx_corner[] = {
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0, 0,
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RPM_SMD_REGULATOR_LEVEL_MIN_SVS, RPM_SMD_REGULATOR_LEVEL_MIN_SVS,
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RPM_SMD_REGULATOR_LEVEL_LOW_SVS, RPM_SMD_REGULATOR_LEVEL_LOW_SVS,
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RPM_SMD_REGULATOR_LEVEL_SVS, RPM_SMD_REGULATOR_LEVEL_SVS,
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RPM_SMD_REGULATOR_LEVEL_SVS_PLUS, RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,
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RPM_SMD_REGULATOR_LEVEL_NOM, RPM_SMD_REGULATOR_LEVEL_NOM,
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RPM_SMD_REGULATOR_LEVEL_NOM_PLUS, RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,
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RPM_SMD_REGULATOR_LEVEL_TURBO, RPM_SMD_REGULATOR_LEVEL_TURBO,
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RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR, RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,
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};
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#endif
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