android_kernel_xiaomi_sm8350/config/lahainaautoconf.h
Meng Wang e92fbc265e soc: swr-mstr-ctrl: Move to CPU-1 FIFO for swr register read/write
Both APSS and ADSP are accessing CPU-0 FIFO when CPS is enabled
during speaker playback. This causes underflow issue when accessing
wsa register from APSS. Move APSS to CPU-1 FIFO to resolve underflow
issue.

Change-Id: I5ed9143bc78757468fbe4bcc686196149ca521f2
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2021-11-03 01:07:29 -07:00

47 lines
1.5 KiB
C

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#define CONFIG_PINCTRL_LPI 1
#define CONFIG_PINCTRL_WCD 1
#define CONFIG_AUDIO_EXT_CLK 1
#define CONFIG_SND_SOC_WCD9XXX_V2 1
#define CONFIG_SND_SOC_WCD_MBHC 1
#define CONFIG_WCD9XXX_CODEC_CORE_V2 1
#define CONFIG_MSM_CDC_PINCTRL 1
#define CONFIG_MSM_QDSP6V2_CODECS 1
#define CONFIG_MSM_QDSP6_APRV2_RPMSG 1
#define CONFIG_SND_SOC_MSM_QDSP6V2_INTF 1
#define CONFIG_MSM_ADSP_LOADER 1
#define CONFIG_REGMAP_SWR 1
#define CONFIG_MSM_QDSP6_SSR 1
#define CONFIG_MSM_QDSP6_PDR 1
#define CONFIG_MSM_QDSP6_NOTIFIER 1
#define CONFIG_SND_SOC_MSM_HOSTLESS_PCM 1
#define CONFIG_SOUNDWIRE 1
#define CONFIG_SOUNDWIRE_MSTR_CTRL 1
#define CONFIG_SND_SOC_WCD_MBHC_ADC 1
#define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1
#define CONFIG_SND_SOC_QDSP6V2 1
#define CONFIG_QTI_PP 1
#define CONFIG_SND_HWDEP_ROUTING 1
#define CONFIG_SND_SOC_MSM_STUB 1
#define CONFIG_SND_SOC_BOLERO 1
#define CONFIG_WSA_MACRO 1
#define CONFIG_VA_MACRO 1
#define CONFIG_RX_MACRO 1
#define CONFIG_TX_MACRO 1
#define CONFIG_SND_SOC_WCD_IRQ 1
#define CONFIG_SND_SOC_WCD938X 1
#define CONFIG_SND_SOC_WCD938X_SLAVE 1
#define CONFIG_SND_SOC_WCD937X 1
#define CONFIG_SND_SOC_WCD937X_SLAVE 1
#define CONFIG_SND_SOC_WSA883X 1
#define CONFIG_SND_SOC_SWR_DMIC 1
#define CONFIG_SND_SOC_LAHAINA 1
#define CONFIG_SND_EVENT 1
#define CONFIG_SND_SWR_HAPTICS 1
#define CONFIG_DIGITAL_CDC_RSC_MGR 1
#define CONFIG_AUXPCM_DISABLE 1
#define CONFIG_SWRM_VER_1P6 1