13 Commits

Author	SHA1	Message	Date
f4exb	6708a6b700	Windows: MSVC2017: changes in sdrbase (1)	2018-11-12 14:04:16 +01:00
f4exb	48cac5385b	PLL lock indication fixes	2018-05-20 03:50:22 +02:00
f4exb	ed08480226	Channel analyzer NG: fixes	2018-05-20 02:24:38 +02:00
f4exb	9f48378677	Channel analyzer NG: return of the lock status indicator and PLL frequency shift for PSK modulated signals	2018-05-18 19:03:54 +02:00
f4exb	e723764376	New PLL: removed locked status heuristics for order > 1	2018-05-17 02:35:06 +02:00
f4exb	c495f82235	Imported Iowa Hills Software IIR and FIR calculator	2018-05-17 00:09:56 +02:00
f4exb	d38d926a87	New PLL: simple FLL code to be put in its own class later	2018-05-16 18:53:16 +02:00
f4exb	a1a2078d7d	New PLL: experimental lock condition algorithm based on phi hat averaging (2) + FLL input and locking mechanixm	2018-05-16 14:20:26 +02:00
f4exb	10c56fc47a	New PLL: experimental lock condition algorithm based on phi hat averaging	2018-05-16 08:42:08 +02:00
f4exb	660d8d22ae	New PLL: heuristics to find locked state	2018-05-16 01:57:16 +02:00
f4exb	bb2d530122	New PLL: phase lock status draft	2018-05-15 19:40:53 +02:00
f4exb	68c50769fe	New PLL: implemented trick on the phase comparator for M-ary PSK operation	2018-05-14 19:14:30 +02:00
f4exb	1549ecaa0f	New PLL with complex signal input and w, zeta, K parameters	2018-05-13 08:55:14 +02:00