This change copies msm_fbdev.c from msm-5.14 kernel, which adds
frame buffer support to display driver. And this file is from
msm-5.4 commit <5fce077d> ("drm: msm: Fix the format prints in
display driver").
Change-Id: I113cb6441334ff6b61cfd15cf863c325d51091b4
Signed-off-by: Kai Xing <quic_kxing@quicinc.com>
Disable DSI ctrl regulator while entering deepsleep and restore
during resume. Refactor deepsleep related code to helper function.
Change-Id: If6da0471db59fbdfa9d9855ee1464fcab90cae15
Signed-off-by: Venkata Prahlad Valluru <quic_vvalluru@quicinc.com>
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
In case of dual dsi usecase, since both the encoders use
the same CTL path, this change ensures that uidle ctl
settings are updated only by the master encoder.
Change-Id: I7bd75ae0195d34f0c1810403fa5e390fbaa64ed0
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change enables minidump for register dumps, debug bus collection
based on CONFIG_QCOM_VA_MINIDUMP config. The minidump driver in 5.4 kernel
needs physical contiguous memory allocation as a requirement. The
minidump collection failure is seen with commit fdf36d7124
("disp: msm: use vzalloc for large allocations") and it uses
vzalloc to address memory allocation failure with order 5. This
patch will disable minidump collection for regdumps, debug bus
to address minidump collection failure.
Change-Id: If5ff91ff95279ee2997765599dbeab16ac2dae60
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This property skips the panel power off for panels
with in-cell design.
Change-Id: I61ff7b8696940b74a58c79eef5b9cd43fd551c01
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
When there is no ulp load entry, ulp load should be set to
enable load.
Change-Id: I531108b4d2137cf9262874bc411ff06592302374
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
Currently we are handling only write command transfer failures from
dsi host transfer path. Modify check to handle read command transfer
failures.
Change-Id: Iee1dbf46a4374819e6d6425eb5acece8ec1fb8b1
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Currently link clk parent set/unset are done as part of dsi_prepare
and dsi_unprepare, but in case of deepsleep with display ON, these
will not be called. Due to mismatch in parent between clk
framework and actual parent, subsequent clk_set_parent will
early return without setting the parent.
To avoid this condition, do set parent to xo, as part of
pm_suspend and restore to link clk source in pm_resume.
Change-Id: I626899304580f9d9fbcc92cd8b139cd89cd48999
Signed-off-by: Venkata Prahlad Valluru <quic_vvalluru@quicinc.com>
It has been observed that TE check may fail even if status read
is passing. Panel detection should be successful only if both
TE check and register read (if supported) pass.
Change-Id: I8d2c5d4139561fe533fc148124b7dde54b63c24e
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
Large allocations using kzalloc can lead to timeouts. This updates
the allocation calls accordingly to use vzalloc to remove
requirements on contiguous memory.
Change-Id: Ica54483787509ed0e9283289fc9d523e8cde9238
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Adjust the data width calculation to reduce the rounding off error
when the widebus is enabled.
Change-Id: Ia2fa4536ce519548989e2befcb22fb685f286c9e
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
When device boots from hibernation, probe function is not called
and rsc need to initialize the hw at the first client update call.
Change-Id: Iba3a3aaebbb8052ce93b8aac1746f33ea80795fb
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
Current logic will unnecessarily call backlight update
twice in cases where backlight level is changing. When
this happens, there is a potential delay waiting for the
first command to complete before sending the second
backlight update with the same value. This change removes
one backlight call and now only calls update if the
property is marked as dirty.
Change-Id: I260f0d73b3a5af9ced7ae261d247595f965a8d9e
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
In DMA start window scheduling, TRIG_CTRL.COMMAND_MODE_DMA_TRIGGER_SEL
is programmed to SW + DMA start window trigger. But if DMS switch
comes after command is scheduled, COMMAND_MODE_DMA_TRIGGER_SEL gets
reprogrammed to SW trigger leading to command transfer failure.
Program the COMMAND_MODE_DMA_TRIGGER_SEL only from the CMD DMA Tx path.
Change-Id: I01062497bb70aa5fdcb25be3715c7cbc4c68b681
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Changes are made to get minimum ib vote for each bus from
device tree entries rather than static values.
Change-Id: Ibecb44ac6b8673c5d5b8979014c215ab3ce9e43f
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Add changes to validate the plane fb_translation mode
and dma_buf flags of drm_gem_obj attached to plane. It
avoids device panic on S2 translation fault and fails the
drm_atomic_commit for which mismatch is detected. In
current codeflow, only S1 mappings are modified when dma_buf
is detached from Non_sec CB and attached to secure SB as part
of msm_gem_get_iova_locked API, but S2 mapping entries are
not modified and this crash is seen.
Change-Id: I6bced92994cd8681cf69231e41bec0c262dafd33
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
The destination format for compressed rgb101010 should be
the same as rgb888. After adding uncompressed RGB101010 support,
the programming for compressed rgb101010 went wrong.
Fix this to re-enable compressed rgb101010 format support.
Change-Id: I805e15df14dda8ff0653a0dba8c4efe3fe0681fd
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Clk framework will cache current parent and skip subsequent
clk_set_parent calls if same parent is set. In case of deepsleep,
clk's parent is reset to xo clks for link clocks but framework
will still see cached parent and skip set_parent call.
To avoid this state, set parent to xo clock for link clocks,
before we enter suspend, so that framework and hw state are
in correct state, when we exit from deepsleep.
Change-Id: Ic7f70ec13497c70a8b4351ebfa49c0db98fc63ab
Signed-off-by: Venkata Prahlad Valluru <quic_vvalluru@quicinc.com>
DCS commands triggered right after timing engine enable can conflict
with blanking period causing command transfer failures. Right after
timing engine enable poll for frame start and line count reaching
active region of display before any DCS commands.
Change-Id: Ia3967e01c3bb5bc82aa3549c300fa8335e00210c
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Add condition to prevent null point dereference.
Change-Id: If6019c0c7035a25ed87afa02c056044c8716bd64
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
If display cont-splash is enabled, then sde irq will be enabled
after registration, but sde power event assumes irq to be disabled
by default and will still try to enable irq with first power event
call, then could cause unbalanced irq enable warning on boot up.
Change-Id: Ic5482dd06501721664994f77cd5764140afb7a62
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
As per HW recommendation, FAL10_VETO_OVERRIDE register can
be programmed to disable FAL10 in alternate to disabling
uidle at the sspp level as disabling UIDLE controller will
only disable DPU traffic shaping and will not stop the
system from entering FAL10 state. This change programs
FAL10_VETO_OVERRIDE register during uidle disable and also
sets CTL_x_UIDLE_ACTIVE register to always one to avoid
race condition between different CTL paths.
Change-Id: I0361543e345bf6c237ad60560e2b11604f5abf92
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
The sde power event function needs to get actual sde kms irq
number to handle irq update call, but it is not able to know
the irq number before irq installation, so move sde power event
call into kms post init to avoid unbalanced irq issues.
Change-Id: Id262b86f98299fbb9a51c9ccb8e68c7bde7f57ed
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
When PM resume commit occurs with mode_changed, enable flag set and
active_changed flag not set, the RM reservation allocated is not cleared
during crtc_destroy_state as encoder_mask in old_crtc_state is NULL.
When there is resume commit from HAL, it polls for this pending reservation
to be cleared causing poll timeouts. This change releases the pending
reservation from the crtc->state->encoder mask, as the old_crtc_state
encoder_mask will be reset with default values at start of PM resume.
Change-Id: Ica1c90a6ea7ef7df08fcb976b6f1b54bbfeea357
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
SDE IRQ callback can run in parallel thread to modeset after removing
pp_done wait before pre_modeset.
If cur_master is cleared in encoder enable function and irq callback
is triggered at the same time, the irq callback could not be handled
properly as cur_master is NULL.So remove clearing cur_master in
encoder enable function to avoid the race condition between modeset
and irq callback.
Change-Id: I2059c699a68838b3c9f6a7dd658a35f178b18c42
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Canceling delayed_off_work in encoder pre_modeset might not be
executed in all cases, but the following encoder enable might
initialize the work.
This will lead to list corruption as delayed_off work list node
is reinitialized before removing from linked list.
Move canceling delayed_off_work to start of encoder mode_set to
ensure work is canceled before reinitialization.
Change-Id: I38687604f2eedced308ea02019c162022725534e
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
During DMS, when tear check registers are updated near
rd_ptr line count, it was resulting in a spurious
rd_ptr_irq to which frame is getting latched and causing
tearing on the screen. This change updates
TEAR_SYNC_WRCOUNT register before disabling the vsync
counter and adds a spinlock to avoid pre-emption.
Change-Id: I986dc3ce6fb3da5fed758c2f50562df44f2ab557
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change updates the single buffer tear check registers
when vsync_in is disabled. It allows mode switch frame
trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <quic_pdhaval@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This change removes tx_wait during DMS for targets which have
dsc_hw_rev_2. For targets with dsc_hw_rev_1, during DMS the
tx_wait is needed since DSC registers are not double buffered
and frame trigger needs to be serialized to avoid pp_timeout
issues.
Change-Id: I46479ed8713602d167e57c9d9d0f800f544607f2
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Avoid irq enable/disable during modeset and trigger
frame as posted start frame. This saves mode_set time
and also avoids unbalanced vblank_irq in this usecase.
Change-Id: I06958da5e52bc2aca0ddc60d2783615f80a839a4
Signed-off-by: Dhaval Patel <quic_pdhaval@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Currently RSC timer register programming is optimized for updating
only during timing param changes and not during RSC state changes
with same timing. Static wakeup time computation should consider
panel jitter for RSC clk state too, else it can result in RSC hang.
This change also removes extra logic for video mode prefil lines
computation for rsc config as video mode does not enable RSC solver.
Current issue scenario exposing the hang is in dual dsi display scenario
where RSC is in clock state and static wakeup time is programmed by
not considering panel jitter, after suspend/pmsuspend while waking up
if RSC switches to command state if primary enabled first and vsync
may arrive much early based on the panel jitter. RSC hw can not handle
if TE arrives earlier than static wakeup time causing RSC hang.
Change-Id: I1434fdd71eb04fdbe22b3601500493c818e9126d
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
The DMA buffer allocation for DSI happens during the first
command transfer. This change moves this allocation to happen during
bind.
Change-Id: I7969a019a8b84282e8a153f5393c9a3de5a28043
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
