Commit Graph

3442 Commits

Author SHA1 Message Date
Meng Wang
795c484ea3 soc: swr-mstr: update logic to dump soundwire register
Some soundwire register dump is skipped with current logic.
Update ppos logic to dump all soundwire registers correctly.

Change-Id: Id053e2b71705ca17caf2de2bb85f8c987790099a
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2020-10-27 11:21:34 +08:00
qctecmdr
7c1dc5a70e Merge "asoc: msm-pcm-q6-v2: Update memset for period size" 2020-10-25 07:34:22 -07:00
qctecmdr
d757a256e4 Merge "asoc: avoid adding global control in loopback probing twice" 2020-10-25 07:34:22 -07:00
qctecmdr
6b3783e3b8 Merge "ASoC: error check for backend index and MCLK src" 2020-10-25 07:34:22 -07:00
qctecmdr
c5337ea009 Merge "asoc: va-macro: Update clk_div switch based on decimation rate" 2020-10-25 07:34:22 -07:00
qctecmdr
3fc43769b0 Merge "asoc: routing: add PRI_TDM path as echo reference data" 2020-10-25 07:34:22 -07:00
qctecmdr
5872bd0838 Merge "asoc: wcd937x: Update slave port config table for BCS" 2020-10-25 07:34:22 -07:00
qctecmdr
93e8156fb8 Merge "asoc: bolero: Add core_vote before gfmux access" 2020-10-25 07:34:22 -07:00
qctecmdr
88318ed5e8 Merge "soc: swr-mstr: Resolve swr overflow, underflow errors for wsa" 2020-10-25 07:34:21 -07:00
qctecmdr
6de6dc28a5 Merge "soc: update port config table to handle sva/voip" 2020-10-25 07:34:21 -07:00
qctecmdr
170e5c6038 Merge "soc: update mechanism to set master port offset1" 2020-10-25 07:34:21 -07:00
qctecmdr
883a10354b Merge "soc: swr-mstr: Check for fifo avail before bulk write" 2020-10-25 07:34:21 -07:00
Mangesh Kunchamwar
b45e776c9c ASoC: error check for backend index and MCLK src
Update proper error checks for backend index and MCLK src
ID.

Change-Id: I36680f7bae66f95f099d59740c68861c5ee28d86
Signed-off-by: Nirav Khatri <khatri@codeaurora.org>
Signed-off-by: Mangesh Kunchamwar <mangeshk@codeaurora.org>
2020-10-22 14:08:51 +05:30
Vignesh Kulothungan
9d8d55d947 soc: update mechanism to set master port offset1
When multiple slave ports are configured to a single master port,
the offset1 of master is the minimum of all slave port's offset1.

Change-Id: I102269806048ecf9982489164a7651a2cdd0661c
Signed-off-by: Vignesh Kulothungan <vigneshk@codeaurora.org>
2020-10-20 11:32:42 -07:00
Laxminath Kasam
b522d6a8f2 asoc: msm-pcm-q6-v2: Update memset for period size
tinycap test can attempt with different size to
read from driver and need to avoid access more
than period size.

Change-Id: Ifa4ddfb086bd83aa981da62e88da3a9395f5aabc
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-10-20 13:18:55 +05:30
Vignesh Kulothungan
d7c3e4fbe1 ASoC: codecs: add null check before use
Add null check for swr dmic component and swr_dmic_priv
before use.
Add array bounds check for slave port index before
accessing the array.

Change-Id: I57cc860e69d75385434822b1975d869d12717de4
Signed-off-by: Vignesh Kulothungan <vigneshk@codeaurora.org>
2020-10-19 23:22:43 -07:00
qctecmdr
19df8856be Merge "asoc: Fix LSM2 mixer control array" 2020-10-19 21:44:04 -07:00
qctecmdr
6e98db9bf4 Merge "asoc: routing: remove unnecessary routing for TDM_TX" 2020-10-19 21:44:04 -07:00
qctecmdr
09d2850b3a Merge "asoc: holi: use new pm_qos API" 2020-10-19 21:44:04 -07:00
qctecmdr
e2c4330a48 Merge "q6afe: add support for lc3 codec playback" 2020-10-19 21:44:03 -07:00
Laxminath Kasam
212d01f856 asoc: wcd937x: Update slave port config table for BCS
Update slave port config table to avoid overlap
of BCS channel with headset ADC2 channel.

Change-Id: Ib414ac1bcbdf66fd4addc6ca22edb78a61ea7a90
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-10-19 13:40:31 +05:30
Guodong Hu
88dba174c9 asoc: avoid adding global control in loopback probing twice
Add condition control to avoid mixer being added twice,
to avoid kernel error printing.

Change-Id: I832e4c08ac06fe885c1497bce4bd4ada96ef83fb
Signed-off-by: Guodong Hu <guodhu@codeaurora.org>
2020-10-19 15:12:21 +08:00
Vatsal Bucha
5936ba71aa soc: swr-mstr: Resolve swr overflow, underflow errors for wsa
SWR overflow, underflow interrupts are seen sometimes on bootup.
Check whether devnum is 0 during fifo read and write. Also assign
read and write fifo depth before master init to resolve errors.

Change-Id: Id7b687985e320396d2f9dab69db56cc7f5426b04
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
2020-10-19 12:04:28 +05:30
Vatsal Bucha
760bd4ab46 soc: swr-mstr: Check for fifo avail before bulk write
Check for fifo availability before writing slave registers
during swrm master bulk write so as to prevent swr
overflow, underflow errors.

Change-Id: I97a914cac289b3f1215ccf5c1abec88b959a9f21
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
2020-10-18 12:45:38 +05:30
Meng Wang
c921bbaee3 asoc: routing: add PRI_TDM path as echo reference data
Add PRI_TDM_TX_0 and PRI_TDM_RX_0 as echo reference data.

Change-Id: Iea5e870e081866f882a3ae5c962d92d7c908ef67
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2020-10-15 14:26:43 +08:00
Laxminath Kasam
180f3f66ae asoc: va-macro: Update clk_div switch based on decimation rate
Update clk_div setting for low power decimations based on
decimation rate instead of lpi flag.

Change-Id: I6e445618af4bf159f3d88a7bc5d07a403a06c1ab
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-10-15 11:25:08 +05:30
Laxminath Kasam
820d1fbf9d asoc: bolero: Add core_vote before gfmux access
GFMUX access happen during RX macro usecase.
Update rx macro to do core_vote before clock
request.

Change-Id: I1afd38ae13066dcfbda307308afce7c4291142d9
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-10-14 20:52:09 +05:30
Laxminath Kasam
e0ea9653c3 asoc: bolero: control wakeup of swr_tx during clock setup
Move the enable and disable of wakeup capability of
swr_tx gpios to clock setup to disable or enable it
in all required usecases.

Change-Id: I9fb76926d8520c382e7f19777190357c50f98994
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-10-14 12:55:12 +05:30
Aditya Bavanari
5712083a09 asoc: Fix LSM2 mixer control array
LSM2 mixer control mapping for VA_CDC_DMA_TX_0
was added in MI2S controls. Move it out to
fix the concurrency issues seen in SVA.

Change-Id: I1e375b2ea86755b935f3d706d2955ad4aa6ef42f
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
2020-10-13 11:59:49 +05:30
Vignesh Kulothungan
941b438117 soc: update port config table to handle sva/voip
Update sample interval in 4.8MHZ port config table of soundwire
digital mic slave and TX1 soundwire master port.
Update the block offset of soundwire digital mics 0 and 3 to handle
voip/sva dmic concurrency in both handset and speaker mode.

Change-Id: I85480c3609a72d4be3c4643b0123f09d71b97fef
Signed-off-by: Vignesh Kulothungan <vigneshk@codeaurora.org>
2020-10-12 15:32:37 -07:00
qctecmdr
1f152bcd76 Merge "asoc: codecs: add sem initialize for blocking notifier." 2020-10-12 10:10:29 -07:00
qctecmdr
ef3408efeb Merge "soc: Add ratelimit to supress the pr_err/dev_err." 2020-10-12 10:10:29 -07:00
qctecmdr
7990d81f20 Merge "ASoC: msm: update quin tdm slot for single lane" 2020-10-12 10:10:29 -07:00
Manisha Agarwal
da866c30a6 q6afe: add support for lc3 codec playback
Add support for lc3 codec playback.

Change-Id: I96ee7bb869c89c71bf8ee986529bf8575efd4b5b
Signed-off-by: Manisha Agarwal <maniagar@codeaurora.org>
2020-10-12 21:39:47 +05:30
qctecmdr
7f2fb6f8ee Merge "dsp: update cal data lock when deregister cvp calibration" 2020-10-12 08:55:34 -07:00
qctecmdr
3da75fbefe Merge "asoc: Add 32bit support in meta i2s" 2020-10-12 08:55:34 -07:00
Meng Wang
a34f3576dc asoc: routing: remove unnecessary routing for TDM_TX
Remove unnecessary routing for TDM_TX to reduce error
log during bootup.

Change-Id: I1e8c9e2caccd77405a82696c86c4cf2ed29c3ce6
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2020-10-12 15:42:06 +08:00
Vangala, Amarnath
aba0be655a asoc: holi: use new pm_qos API
This change ensure all concurrent low latency/
 ultra low latency use cases run on core 1 and 2.

Change-Id: I187787ea609768bbfb6098a844dab4ebef611a9c
2020-10-08 14:00:47 +05:30
Meng Wang
dfa3df69ae asoc: bolero: update logic for va clk switch on bolero 2.1
On bolero 2.1, SVA switch is not retain at VA_CLK
when switch between handset and headset mic sva.
Update the clock release logic during swr power event.

Change-Id: I62b492dcbff4b4f3249d1a6b3b792690b5b5c27c
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2020-10-07 22:53:24 +05:30
Prasad Kumpatla
0538f8320d asoc: codecs: add sem initialize for blocking notifier.
add semaphore initialize for the notifier before the blocking
notifier.

Change-Id: I20a919215fdc0da1830368070063fbe2b8fc5f62
Signed-off-by: Prasad Kumpatla <nkumpat@codeaurora.org>
2020-10-07 07:01:45 -07:00
qctecmdr
ab02a0d9c1 Merge "dsp: Add param header size based on the instance id support" 2020-10-07 01:58:57 -07:00
qctecmdr
3da951c1fe Merge "ASoC: bolero: Make tx swr gpio as wakeup capable" 2020-10-07 01:58:57 -07:00
qctecmdr
80e8add847 Merge "asoc: msm: add routing rules for QUIN_AUX_PCM" 2020-10-07 01:58:57 -07:00
qctecmdr
ddba57b58c Merge "asoc: wcd938x: move 500ms after dev_up sets to true" 2020-10-07 01:58:57 -07:00
qctecmdr
7aa70c8010 Merge "ASoC: codecs: add null check before use" 2020-10-07 01:58:57 -07:00
qctecmdr
6f61b0015c Merge "soc: fix HS LPI issue for holi target" 2020-10-07 01:58:57 -07:00
qctecmdr
3df4c1d586 Merge "dsp: add change to handle use-after-free in cal_utils_is_cal_stale" 2020-10-07 01:58:57 -07:00
qctecmdr
945c14f7a8 Merge "dsp: check speaker index before accessing array" 2020-10-07 01:58:57 -07:00
Deeraj Soman
2844b41480 asoc: Add 32bit support in meta i2s
Add 32bit PCM support in META I2S

Change-Id: I9dc09f853858f09a8bcd0a6529416abf1e159e71
Signed-off-by: Deeraj Soman <sdeeraj@codeaurora.org>
2020-10-06 23:33:36 -07:00
Prasad Kumpatla
a07613afcd soc: Add ratelimit to supress the pr_err/dev_err.
Add ratelimit to supress the logs flooding at the
time of SSR.In all places defined ratelimit as,
in 1sec one debug msg prints.

Change-Id: I6dfe140848e5cecb1b311c432f8311cdf0615a58
Signed-off-by: Prasad Kumpatla <nkumpat@codeaurora.org>
2020-10-07 10:21:42 +05:30